跳到主要內容

臺灣博碩士論文加值系統

(44.200.30.73) 您好!臺灣時間:2022/08/11 03:26
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:李家慶
研究生(外文):Chia-Ching Li
論文名稱:5.2GHz互補式金氧半電晶體低雜訊放大器之設計與分析
論文名稱(外文):The Design and Analysis of 5.2 GHz CMOS Low Noise Amplifier
指導教授:龔 正
指導教授(外文):Jeng Gong
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:109
中文關鍵詞:低雜訊放大器
外文關鍵詞:Low Noise Amplifier
相關次數:
  • 被引用被引用:1
  • 點閱點閱:185
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
在這近十年來,可攜式的無線通訊產品已快速大量的成長及應用。而在高資料傳輸率的無線區域網路(WLAN)通訊系統之中,有IEEE802.11a與HIPERLAN兩個系統規格。這兩個系統均操作於5.15-5.35 GHz和5.47-5.725 GHz的5Ghz頻帶上。此外,為了達到高度積體化與低價的需求,射頻前端接收機的電路設計早已被鎖定在以互補式金氧半電晶體的積體電路製程來實現。而在此射頻接收機中,須要一個良好特性的低雜訊放大器。在此篇論文中,我們將其操作的中心頻率設定在5.2GHz。
在此低雜訊放大器的設計中,我們使用 RF/Mixed 0.18μm的互補式金氧半積體電路製程,在模擬工具上,使用安捷倫公司(Aligent)的ADS 1.5版進行高頻電路摸擬。首先,在一個單級的疊接(cascode)低雜訊放大器中,經由小訊號的公式推導,我們發現在無基體效應(body effect)之下會比在有基體效應的影響下,功率增益(S21)會較大而其雜訊指數(NF)會較小。然後,在經由軟體的摸擬驗證,在1.8V的電壓供應中,有基體效應的單級疊接低雜訊放大器,其NF=2.3 dB, S21=12.506dB, 輸入三次方交點(IIP3)=1dBm;然而在無基體效應影響下,其NF=1.939dB, S21=16.061dB, IIP3=-9.7 dBm。
除此之外,我們以單級疊接方式的低雜訊放大器為基礎,提出其拓撲架構來改善基體效應及提高其他操作特性。一個較低雜訊的疊接低雜訊放大器中,其NF=1.989dB,S21=15.206dB,IIP3=-3dBm;而一個極低功率消耗的疊接低雜訊放大器中,只有4.914mW的功率消耗,S21=15.167dB,NF=2.443dB;另一個低供應電壓的疊接低雜訊放大器中,其操作電壓只須一伏特,而其NF=2.079dB,S21=15.030dB。

In the recent ten years, the rapid growth of wireless portable communication products has led to numerous developments. There are two high speed data rate wireless local area network (WLAN) communication systems which are the IEEE802.11a and HIPERLAN. They are operated in the 5-GHz frequency band (5.15-5.35/5.47-5.725 GHz). In order to achieve the high integrated density and low cost, the radio frequency (RF) front-end has caught the attention in standard CMOS technology. A CMOS RF receiver needs a high performance low noise amplifier (LNA) and we set the center frequency at 5.2GHz, in this thesis.
The LNAs designed in this thesis, used a RF/Mixed Mode 0.18μm CMOS process technology. The simulation tool is ADS 1.5 of Aligent. Firstly, we provide the equations of single stage cascode LNA voltage gain with and without body effect. We found that the gain is higher and noise figure is lower without body effect. Secondly, assume at the same power consumption, in the cascode circuit with body effect, at 1.8V supply voltage, the noise figure is 2.3dB, power gain is 12.506 dB, and IIP3=1dBm; the noise figure is 1.939dB, power gain is 16.061dB, but the IIP3=-9.7dBm.
In addition, we propose some other cascode LNA topologies to improve the body effect and enhance the performances. A lower noise cascode LNA which has NF=1.989dB, S21=15.206dB, and IIP3=-3dBm; an ultra low power dissipation LNA which has just 4.914mW, and NF=2.443dB, S21=15.167dB; and a low supply voltage cascode LNA which has just only 1V, and NF=2.079dB, S21=15.030dB.

Contents
Chapter1 Introduction..............................................................................1
1.1 Motivation.................................................................................................1
1.2 Organization..............................................................................................3
Chapter2 The Fundamentals of LNA in RF Design................................4
2.1 The Role of LNA in Front-end Receiver...................................................4
2.1-1 Heterodyne Front-end Receiver................................................................4
2.1-2 Direction Conversion Front-end Receiver................................................6
2.1-3 Image-Reject Front-end Receiver.............................................................6
2.2 Design Parameters of LNA........................................................................8
2.2-1 S-parameters.............................................................................................8
2.2-2 Noise Figure (NF).....................................................................................9
2.2-3 Linearity (P-1db, IIP3)............................................................................11
2.2-4 Sensitivity................................................................................................14
2.2-5 Dynamic Range (DR).............................................................................15
2.2-6 Stability Factor (K).................................................................................16
2.2-7 Power Gain & Power Dissipation...........................................................17
2.3 The Input Impedance Matching Architectures of LNA...........................18
2.3-1 Resistive Termination.............................................................................18
2.3-2 1/gm Termination....................................................................................19
2.3-3 Shunt-Series Feedback............................................................................20
2.3-4 Inductive Degeneration...........................................................................20
2.4 Summary of Recent LNA Research........................................................22
Chapter3 Noise Analysis in LNA Design.............................................23
3.1 Fundamental Noise Concepts..................................................................23
3.1-1 Noise Definition......................................................................................23
3.1-2 Noise Characteristics Description...........................................................24
3.1-3 Noise Transformation..............................................................................25
3.1-4 Noise Correlation and Un-correlation.....................................................25
3.1-5 Input-referred Noise................................................................................26
3.2 Noise Source............................................................................................27
3.2-1 Thermal Noise.........................................................................................27
3.2-2 Flicker Noise (1/f Noise) .......................................................................33
3.2-3 Shot Noise...............................................................................................34
3.2-4 Burst Noise (Popcorn Noise) .................................................................35
3.3 Noise Performance of Inductive Degeneration LNA..............................36
3.4 Noise Optimization Method....................................................................40
Chapter4 The Analysis and Design of Cascode LNA...........................44
4.1 The First Order Small Signal Analysis....................................................44
4.2 The Second Order Small Signal Analysis...............................................50
4.3 Analysis of the Gain and Noise of the Circuit with Body effect.............56
4.4 The Cascode LNA Circuit Design with Body effect #1..........................60
4.4-1 Design Considerations of Cascode LNA with Body effect....................60
4.4-2 Simulation Results of Cascode LNA with Body effect..........................63
4.5 The Cascode LNA Circuit Design with no Body effect #2.....................67
4.6 The Discussions of Cascode LNA...........................................................72
4.7 Effect of the Q value of Inductor on Cascode LNA................................76
Chapter5 The Topological Structures of Cascode LNA........................79
5.1 Reduced Channel Resistance Noise of Cascode LNA............................79
5.2 Low Noise of Cascode LNA-Circuit #3..................................................81
5.3 Low Power of Cascode LNA-Circuit #4.................................................88
5.4 Low Voltage of Cascode LNA-Circuit #5...............................................95
Chapter6 Conclusions..........................................................................104
References..............................................................................................106

[1] Ting-Ping, and Eric Westerwick, “5-GHz CMOS Radio Transceiver Front-End Chipset”, IEEE Journal of Solid-State Circuits, vol.35, no.12, pp.1927-1933, December 2000.
[2] Thomas H. Lee, Hirad Samavati, and Hamid R. Rategh, “5-GHz CMOS Wireless LANs”, IEEE Transactions Microwave Theory and Techniques, vol.50, no.1, pp.268-280, January 2002.
[3] Hossein Hashemi, and Ali Hajimiri, “Concurrent Multiband Low-Noise Amplifiers-Theory, Design, and Applications”, IEEE Transactions Microwave Theory and Techniques, vol.50, no.1, pp.288-301, January 2002.
[4] J. Crols and M. Steyaert, “CMOS Wireless Transceivers”, Kluwer Academic Publishers, 1997.
[5] Andrew N. Karanicolas, “A 2.7-V 900MHz CMOS LNA and Mixer”, IEEE Journal of Solid-State Circuits, vol.31, no.12, pp.1939-1944, December 1996.
[6] Behzad Ravavi, “RF Microelectronics”, Prentice-Hall, Inc. 1998.
[7] Asad A. Abidi, “Direct-Conversion Radio Transceivers for Digital Communications", IEEE Journal of Solid-State Circuits, vol.30, no.12, pp.1399-1410, December 1995.
[8] Jacques C. Rudell, Jia-Jiunn Ou, Thomas Byunghak Cho, Geoerge Chen, Francesco Brianti, Jeffrey A. Weldon, “A 1.9-GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Applications”, IEEE Journal of Solid-State Circuits, vol.32, no.12, pp.2071-2088, December 1997.
[9] Kai Chang, “Microwave Solid-State Circuits and Applications", John Wiley & Sons, Inc. 1994
[10] Paul H. Young, “Electronic Communication Techniques”, Prentice Hall International, Inc. Fourth Editioin1999.
[11] Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits”, 0Cambridge University Press, 1998.
[12] David A. Jonhs, Ken Matrin, “Analog Integrated Circuit Design” John Wiley & Sons, Inc. 1997.
[13] J. Y.-C. Chang, Asad A. Abidi, “Large Suspended Inductors on Silicon and Their Use in a 2μm CMOS RF Amplifier”, IEEE Electron Device Letters, vol.14, no.5, pp.246-248, May 1993.
[14] Ahmadreza Rofougaran, James Y.-C. Chang, Maryam Rofougaran, and Asad A. Abidi, “A 1GHz CMOS RF Front-End IC for a Direct-Conversion Wireless Receiver”, IEEE Journal of Solid-State Circuits, vol.31, no.7, pp.880-889, JULY 1996.
[15] Samuel Sheng, Lapoe Lynn, Jim Peroulas, Kevin Stone, Ian O’Donnell, Robert Brodersen, “A Low-Power CMOS Chipset for Spreda-Spectrum Communications”, IEEE Internal Solid-State Circuits Conference, pp.346-348, 1996.
[16] Eric H. Westerwick, “A 5-GHz Band CMOS Low Noise Amplifier with a 2.5-Db Noise Figure”, IEEE, pp.224-227, 2001.
[17] J. C. Huang, Ro-Min Weng, Cheng-Chin Chang, Kang Hsu, and Kun-Yi. Lin, “A 2V 2.4 GHz Fully Integrated CMOS LNA”, IEEE, pp.IV-466-IV469, 2001.
[18] Chih-Chun Tang and Shen-Iuan Liu, “Low-Voltage CMOS Low-Noise Amplifier using Planar-Interleaved Transformer”, Electronics Letters, vol.37, no.8, pp.497-498, 12th April 2001.
[19] Ramez A. Rafla and Mourad N. El-Gamal, “Design of A 1.5V CMOS Integrated 03 GHz LNA”, IEEE, pp.II-440-II443, 1999.
[20] Hong-Sun Kim, Xiaopeng Li, and Mohammed Ismail, “A 2.4GHz CMOS Low Noise Amplifier using an Inter-stage Matching Inductor”, IEEE, pp.1040-1043, 1999.
[21] Brian A. Floyd, Jesal Mehta, Carlos Gamero, and Kenneth K. O, “A 900-MHz, 0.8-μm CMOS Low Noise Amplifier with 1.2-Db Noise Figure”, IEEE Custom Integrated Circuit Conference, pp.661-664, 1999.
[22] Qiuting Huang, Paolo Orsatti, Francesco Piazza, “Broadband, 0.25μm CMOS LNAs with Sub-2Db NF for GSM Applications”, IEEE Custom Integrated Circuit Conference, pp.67-70, 1998.
[23] Eyad Abou-Allam and Tajinder Manku, “A Low Voltage Design Technique for Low Noise RF Integrated Circuits”, IEEE, pp.IV-373-377, 1998.
[24] Yongmin Ge and Kartikeya Mayaram, “A Comparative Analysis of CMOS Noise Amplifier for RF Applications”, IEEE, pp.IV-349-352, 1998.
[25] Derek K. Shaeffer and Thomas H. Lee, “A 1.5V, 1.5GHz CMOS Low Noise Amplifier”, Symposium on VLSI Circuits Digest of Technical Papers, pp.32-33, 1996.
[26] C. D. Motchenbacher, J. A. Connelly, “Low-Noise Electronic System Design”, John Wiley & Sons, Inc. 1993.
[27] Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, McGraw-Hill Previews Edition 2000.
[28] A. Van Der Ziel, “Noise in Solid State Device and Circuits”, 1986.
[29] Paul R. Gray, Robert G. Meyer, “Analysis and Design of Analog Integrated Circuits”, John Wiley & Sons, Inc. Third Edition 1993.
[30] Willy Sansen, Rudy J. Van De Plassche, and Johan H. Huijsing, “Analog Circuit Design- MOS RF Circuits, Sigma-Delta Converters and Translinear Circuits”, Kluwer Academic Publishers.
[31] Derek K. Shaeffer and Thomas H. Lee, “A 1.5V, 1.5GHz CMOS Low Noise Amplifier”, IEEE Journal of Solid-State Circuits, vol.32, no.5, pp.745-759, May 1997.
[32] Behzad Razavi, “CMOS Technology Characterization for Analog and RF Design”, IEEE Journal of Solid-State Circuits, vol.34, no.3, pp.268-276, March 1999.
[33] Yi Lin, Michael Obrecht, and Tajinder Manku, “RF Noise Characterization of MOS Devices for LNA Design Using a Physical-Based Quasi-3D Approach”, IEEE Transactions on Circuits and Systems-П: Analog and Digital Signal Processing, vol.48, no.10, pp.972-984, October 2001
[34] Zhong Yuan Chang and Will M. C. Sansen, “Low-Noise Wide-Band Amplifiers in Bipolar and CMOS Technologies”, Kluwer Academic Publishers, 1991.
[35] Reinhold Ludwig, Pavel Bretchko, “RF Circuit Design Theory and Applications”, Prentice-Hall, Inc. 2000.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top