臺灣博碩士論文加值系統

隨著通訊市場在近幾年來的巨幅成長，無線通訊領域的發展也相當迅速。加上製程技術不斷地進步，以前必須採用GaAs、BiCMOS或SiGe製程的RF(radio frequency) IC部分，現在也可以利用標準的CMOS製程來完成。目前市面的產品都走向低成本、低功率的訴求。RF IC、IF(intermediate) IC和基頻(baseband)電路的整合，可省去包裝的費用及時間，大幅降低成本、增加產能和縮小晶片面積。將所有電路整合到單一晶片上，也是未來積體電路設計的趨勢之一。
在5GHz頻段的無線通訊系統大致有兩種不同規格：歐洲體系為HIPERLAN (High Performance Radio LAN)系統；美國體系為IEEE 802.11a 系統。目前RF前端接收器主要包括幾個部分：低雜訊放大器(low noise amplifier, LNA)、混波器(Mixer)、壓控振盪器(voltage-controlled oscillator, VCO)等部分。壓控振盪器的主要功能為提供混波器一個參考訊號，將高頻訊號降頻至基頻，再輸入後級的數位電路作訊號處理。在本篇論文中，我們利用0.18um CMOS製程來模擬與分析壓控振盪電路的特性。另外我們也對電感Q值和功率消耗對振盪電路的影響加以探討。最後提出一些在電路上的改良架構，並比較其優缺點。
在本篇論文中，我們利用0.18微米金氧半製程來設計5GHz無線傳輸的振盪器電路。使用的模擬軟體為ADS(Advanced Design System) 1.5系統。首先，先介紹振盪器電路中的基本元件，以及這些元件工作於高頻時的特性。振盪器電路架構是雙端輸出，其輸出為差動訊號，相位差180度。第二，振盪器的相位雜訊為RF 接發器中的重要設計考量之一。在論文中，我們利用Lesson模型和time-variant模型來分析相位雜訊。此外，電感的Q值也是影響相位雜訊的重要因素。根據數學公式的推導和模擬的結果，當製程技術更加進步，則電感的Q值得以改善，電路的相位雜訊也會降的更低。在振盪器電路中，主要的取捨為功率消耗和相位雜訊。相位雜訊的特性和功率消耗成反比。要得到低相位雜訊，便必須消耗較大的功率。最後，我們提出了一個新的架構。新架構可以產生一個很大的負電阻，使得整體電路可以更快穩定。

In this thesis, 0.18μm CMOS technology is used to design oscillators working at 5GHz for wireless applications. The simulation tool used is the ADS 1.5. At first, we introduce the fundamental components of oscillator, and discuss their behaviors in RF band. The architectures of oscillator are cross-coupled pair and complementary cross-coupled pair. The output signal is in differential form. Phase noise is an important factor of oscillator in RF transceiver systems. Therefore, Lesson model and time-variant model are used to analyze. The Q-value, quality factor, of inductor is very significant to phase noise. According to the mathematic equations and simulation results, more advanced process technology gives better quality factor of inductor and phase noise. In LC oscillator circuit, the main trade off is between power consumption and phase noise. The phase noise is inversely proportional to power consumption. At last, a new structure that can generate higher negative resistance is proposed. It allows the circuit take less time to stable.

目錄
第一章 緒論 ……………………………………………………… 1
1.1 研究動機 ……………………………………………………… 1
1.2 論文架構 ……………………………………………………. 1
第二章 振盪器之設計考量、原理與背景回顧 ……………. 3
2.1 振盪器之設計考量 …………………………………………… 3
2.2 振盪器原理簡介 ……………………………………………… 4
2.2.1 並聯回授(Shunt Feedback) …………………………………… 4
2.2.2 串聯回授(Series Feedback) …………………………………... 5
2.2.3 Quality factor ………………………………………………… 5
2.3 壓控振盪器之電感 …………………………………………… 6
2.4壓控振盪器之變容器(Varactor) ………………………………… 7
2.4.1 MOS變容器 …………………………………………………. 8
2.4.2 反轉型變容器(Inversion-mode Varactor) ……………………... 9
2.4.3 P-N型變容器 ………………………………………………... 9
2.4.4 聚積型變容器(Accumulation-mode varactor) ……………… 10
2.5壓控振盪器之背景回顧 …………………………………………………………………... 11
第三章 VCO之相位雜訊(Phase Noise)分析 ……………… 26
3.1 相位雜訊簡介 ………………………………………………… 26
3.1.1 相位雜訊在通訊系統中的影響 …………………………….. 26
3.1.2 相位雜訊之基本定義 ……………………………………… 27
3.2 線性非時變 Leeson相位雜訊模型 ………………………… 28
3.3 時變相位雜訊模型 …………………………………………… 30
3.3.1 雜訊對振盪系統中振幅及相位之影響 …………………….. 30
3.3.2 LC振盪器之ISF( Impulse Sensitivity Function ) …………… 31
3.3.3 電流-相位轉換和相位-電壓轉換 ………………………… 32
第四章 VCO電路設計與分析 ………………………………... 47
4.1 VCO之電路基本架構 ………………………………………… 47
4.1.1 VCO電路簡介 ……………………………………………… 47
4.1.2 VCO電路結構分析 ………………………………………… 47
4.2 互補式cross-coupled VCO模擬與分析 ……..…………….. 51
4.2.1 基本架構之Cross-coupled VCO模擬與分析 ……….…… 51
4.2.2 改良之Cross-coupled VCO模擬與分析 ……………………. 53
4.3 Cross-coupled VCO模擬與分析 ……………………………… 53
4.4 電感Q值對VCO電路之影響 …………………………........... 55
4.5 振幅、功率消耗和相位雜訊之設計考量 ……………….......... 56
4.4 負電阻電路之探討 …………………………………………… 58
4.4.1 負電阻電路工作基本原理 ……………………………… 58
4.4.2 負電阻電路之應用 ………………………………………. 59
第五章 結論 ……………………………………………………… 83

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