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研究生:高小文
研究生(外文):Kao Shiau Wen
論文名稱:低電壓(1.5V)8位元50MS/s類比數位轉換器使用0.35um1P4MCMOS製程
論文名稱(外文):Low Voltage(1.5V) 8bit-50MS/s Analog-to-Digital Converter on 0.35um 1P4M CMOS Technology
指導教授:徐永珍徐永珍引用關係
指導教授(外文):Klaus Yung-Jane Hsu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:81
中文關鍵詞:低電壓類比數位轉換器
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隨著超大型積體電路製程不斷縮小化、操作電壓不斷下降,對於數位電路而言有著功率消耗下降的優點。然而對於類比電路而言卻不盡然,不僅在維持相同動態範圍(Dynamic Range)下,功率消耗隨操作電壓下降而上升,且電晶體尺寸縮小化直接造成其輸出阻抗下降,如何維持相同的電壓增益便成為一個需要被解決的課題。短通道電晶體與長通道電晶體特性並不全然相同,因此許多在以往設計中所遵守的設計準則需要被適度的修正以因應短通道電晶體的工作特性。本文針對以往設計放大級時採用負電導耦合對必須遵守的迴授電導與負載電導之電導比小於0.9的準則提出修正,並且以此修正方式設計一適用於低電壓(1.5V)8位元50MS/s類比數位轉換器使用0.35um CMOS 1P4M Technology之全差動放大器。本文修正方式在完全多不耗費晶片面積與功率消耗下,較以往設計準則增加約20dB低頻開迴路增益且不影響其單一增益頻率。但利用此方式設計,對於低頻開迴路增益的有效控制有一定程度的影響所以需多增加安全範圍以利整體效能達到預期。同時本文以此放大器設計一低電壓(1.5V)8位元50MS/s脈管式類比數位轉換器。本文採每單級1.5位元,共8級。為避免功率消耗增加過大,在每單級1.5位元的架構上做改善,可節省2個比較器與2個鎖相器的功率消耗。如此由Hspice模擬並由Matlab做DFT分析結果可得本文設計在輸入頻率為20MHz且取樣頻率為50MHz的條件下,有效位元數(ENOB)大於7位元。
第一章 序論
第一節 相關研究發展現況及研究動機………………………………....…...….1
第二節 論文概述………………………………………………………….….…..4
第二章 脈管式類比數位轉換器架構概論
第一節 類比數位轉換器設計相關的特性參數…………………..………...….5
第二節 脈管式類比數位轉換器之架構與原理…………………………...…...9
第三節 誤差修正與單級1.5位元(1.5bit/stage)工作原理……………...……14
第三章 全差動運算放大器(Fully Differential Operational Amplifier)之設計
第一節 低電壓設計所面臨之挑戰……………………………………………..20
第二節 提出修正傳統設計準則……………..………………………………..24
第三節 設計符合8位元50MS/s類比數位轉換器使用之全差動運算放大器.29
第四節 全差動運算放大器之模擬結果………………………………………..34
第四章 低電壓(1.5V)8位元50MS/s類比數位轉換器
第一節 概括介紹本文所設計之低電壓8位元50MS/s類比數位轉換器…….41
第二節 類比電路部分之設計及模擬結果……………………………………..49
前端取樣保留電路及模擬結果……………………………………….49
電位倍增電路及模擬結果…………………………………………….58
比較器及模擬結果…………………………………………………….60
參考電位電路………………………………………………………….63
第三節 數位電路部分之設計及模擬結果…………………………………......64
編碼器及模擬結果…………………………………………………….64
鎖相器及模擬結果…………………………………………………….66
加法器及模擬結果…………………………………………………….68
第四節 8位元50MS/s類比數位轉換器之模擬結果………………………….71
第五章 討論與後續研究建議
討論與後續研究建議……………………………………………………………76
參考文獻…………………………………………………………………………...77
附錄
[01] B. Razavi, Principle of Data Conversion System Design, IEEE Press, 1995
[02] Tanja C. Hofner, “ Defining And Testing Dynamic ADC Parameters”, Microwave & RF, pp.75-94, 2000
[03] Y. Nejime, M. Hotta, and S. Ueda, ” An 8-b ADC with over-Nyquist input at 300-Ms/s conversion rate”, IEEE Journal of Solid-State Circuits, Vol. 26, No. 9, pp. 1302 —1308, September 1991
[04] C. W. Moreland, “An 8b 150 MSample/s serial ADC”, Digest of Technical Papers, 41st IEEE International Solid-State Circuits Conference (ISSCC), pp. 272 —273, 1995
[05] B. Brandt and J. Lutsky, “A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bits at Nyquist”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 12, pp. 1788 —1795, December 1999
[06] H. Van Der Ploeg and R. Remmers, "A 3.3 V 10 b 25 Msample/s two-step ADC in 0.35 μm CMOS ", IEEE Journal of Solid-State Circuits, Vol. 34, No. 12, pp. 1803 — 1811, December 1999
[07] P. Vorenkamp and J. P. M. Verdaasdonk, “A 10 b 50 MS/s pipelined ADC”, Digest of Technical Papers, 39th IEEE International Solid-State Circuits Conference (ISSCC), pp. 32 —33, 1992
[08] T. B. Cho and P. R. Gray, ” A 10-bit, 20-MS/s, 35-mW pipeline A/D converter”, Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 499 —502, 1994
[09] K. Y. Kim, N. Kusayanagi, and A. A. Abidi, “A 10-bit, 100 MS/s CMOS A/D Converter”, Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 419 —422, 1996
[10] Y. —T. Wang and B. Razavi, “An 8-bit 150-MHz CMOS A/D converter”, IEEE Journal of Solid-State Circuits, Vol. 35, No. 3, pp. 308 —317, March 2000
[11] S. H. Lewis, ‘‘Optimizing the stage resolution in pipelined, analog-to-digital converters for video-rate applications’’, IEEE Transactions on Analog and Digital Signal Processing Circuits and Systems II, Vol. 39, No. 8, pp. 516 — 523, August 1992
[12] J. H. Hall and D. G. Nairn, “A 100 mW 10 bit 100 MS/s all CMOS ADC”, Third International Conference on Advanced A/D and D/A Conversion Techniques and Their Applications, pp. 5 —8, 1999
[13] I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC”, IEEE Journal of Solid-State Circuits, Vol. 35, No.3, pp. 318—325, 2000
[14] Y. —M. Lin, B. Kim, and P. R. Gray, “A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS”, IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, pp. 628 —636, April 1991
[15] J. Fernandes, S. R. Lewis, A. M. Mallinson, and G. A. Miller, “A 14-bit 10-μs subranging A/D converter with S/H”, IEEE Journal of Solid-State Circuits, Vol. 23, No. 6, pp. 1309 —1315, December 1988
[16] D. A. Mercer, “A 12-b 750-ns subranging A/D converter with self-correcting S/H”, IEEE Journal of Solid-State Circuits, Vol. 26, No. 12, pp. 1790 —1799, December 1991
[17] Andrew M. Abo and Paul R. Gray, “ A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, pp. 599 -606, May 1999
[18] Jie Yan and Randall L. Geiger, “ A Negative Conductance Voltage Gain Enhancement Technique for Low Voltage High Speed CMOS Op Amp Design”, pp.502 —505, IEEE 2000
[19] Mezyad M. Amourah and Randall L. Geiger, “ Gain and Bandwidth Bootsting Techniques for High-Speed Operational Amplifiers”, pp. i232 —i235, IEEE 2001
[20] Klaas Bult and Govert J. G. Geelen, “A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain”, IEEE Journal of Solid-State Circuits, Vol. 25, No. 6, pp. 1379 -1384, December 1990
[21] David J Allstot, “A Precision Variable-Supply CMOS Comparator”, IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 6, pp. 1080 -1087, December 1982
[22] Behzad Razavi, Design of Analog CMOS Integrated Circuits, 2000
[23] Roubik Gregorian, Analog MOS Integrated Circuits for Signal Processing, 1986
[24] Yong-In Park and Eduardo Bartolome, “ A Low Power 10 bit, 80 MS/s CMOS Pipeline ADC at 1.8V Power Supply”, pp. i580 —i583, IEEE 2001
[25] Takeshi Sigenobu and Takahiro Miki, “An 8-bit 30MS/s 18mW ADC with 1.8V single power supply”, SVLC, pp. 209 —201, 2001
[26] Jun Ming and Stephen H. Lweis, “ An 8-bit 80-Msamples/s Pipeline Analog to Digital Converter With Background Calibration”, IEEE Journal of Solid-State Circuits, Vol. 36, No. 10, pp. 1489 -1497, May 2001
[27] Yun-Ti Wang and Behzad Razavi, “ An 8-Bit 150-MHz CMOS A/D Converter”, IEEE CICC, pp.117 —120, 1999
[28] W. Bright, “ 8b 75Msample/s 70mW Parallel Pipelined ADC Incorporating Double Sampling”, ISSCC, pp.146 —148, 1998
[29] Myung-Jun Choe and Band-Sup Song, “ An 8b 100Msample/s CMOS Pipelied Folding ADC”, SVLC, pp.81 —82, 1999
[30] John B. Hughes and Martin Mee, “ A Low Voltage 8-Bit, 40MS/s Switched-Current Pipeline Analog-to-Digital Converter”, IEEE, pp. i572 —i575 2001
[31] Babak Nejati and Omid Shoaei, “ A 10-Bit, 2.5-V, 40Msample/s, Pipelined Analog-to-Digital Converter in 0.6-um CMOS”, IEEE, pp.i576 —i579, 2001
[32] Sotoudeh Hamedi-Hagh and C.A.T. Salama, “ A 10Bit, 50Msample/s, Low Power Pipelined A/D Converter for Cable Modem Applications”, IEEE, pp. i424 —i427, 2001
[33] A.G. Andreou, Low-Voltage/Low-Power Integrated Circuits and Systems, 1998
[34] Jian-Bang Lin, “ Design of 10-bit, 20MHz Sampling Rate CMOS Pipelined Analog-to-Digital Converter”, thesis, 2001
[35] Roubik Gregorian, Introduction to CMOS Op-Amps and Comparators, 1999
[36] Vincenzo Peluso, Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters, 1999
[37] Rudy J. Van De Plassche, Analog Circuit Design (Low-Power Low-Voltage, Integrated Filters and Smart Power), 1995
[38] David Johns, Analog Integrated Circuit Design, 1997
[39] Henrik Sjoland, High Linear Integrated Wideband Amplifiers, 1999
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