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研究生:蘇明俊
研究生(外文):Ming-Chun Su
論文名稱:一個工作在1.5伏特2.4G赫茲非整數型頻率合成器
論文名稱(外文):A 1.5V 2.4GHz Fractional-N Frequency Synthesizer
指導教授:徐永珍徐永珍引用關係
指導教授(外文):Klaus Y. J. Hsu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:64
中文關鍵詞:頻率合成器射頻前端電路接收器電路設計鎖相迴路壓控震盪器相位雜訊分析非整數型多係數除頻器
外文關鍵詞:Frequency SynthesizerRF front-end systemreceiver circuit designPhase Lock Loopvoltage-controlled oscillatorphase noise analysisFractional-Nmulti-modulus divider
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行動通訊在近年來的市場成長,已經引起全世界電子業及通訊產業的高度興趣,為了達到wireless any time and any where 世界各大廠商無不利用IEEE所規範的免付費頻段(ISM band)進行開發各種通訊規格,在無線通訊區域網路(WLAN,Wireless Local Area Network)規格中,IEEE 802.11b,Blue tooth和HomeRF皆為其中常見的通訊規格。以802.11b為例,近年來已被無線區域網路廣泛使用。它採用了2.4GHz的ISM頻帶,使用的頻率範圍為2.4 ~ 2.4835 GHz,提供的資料傳輸速率(Data Rate)為 1 ~ 2 Mbits/sec。
為了可攜性跟低成本的要求,CMOS可以說是實現射頻前端電路最恰當的選擇,雖然Bipolar和GaAs較CMOS而言,有較佳的高頻表現,但隨著製程技術的演進以及電路設計的改善,CMOS製程在射頻前端電路的應用上依然大有可為。
其中頻率合成器(Frequency Synthesizer)是RF收發器的關鍵元件之一,它提供混波器在升降頻時所需要的精確頻率。在今日可攜式產品大幅成長的情形下,設計的原則是低成本、低功率消耗、及高度的整合性。除此之外,設計頻率合成器時尚需考量相位雜訊(Phase Noise)、轉換速度(Switching Speed)與頻率解析度(Frequency Resolution)等問題。
在傳統的頻率合成器設計中是以整數型鎖相迴路為主,但是此種電路型態必須在頻率解析度(Frequency Resolution)與迴路頻寬(Loop Bandwidth)之間有所取捨 ,在頻率解析度的限定之下,迴路頻寬是受到限制的。然而較寬的迴路頻寬才能夠提供較快的轉換速度,因此整數型頻率合成器並無法同時提供好的頻率解析度及快速的轉換速度。
基於上述理由,本論文中採用了非整數型的設計架構(Fractional-N Frequency Synthesizer),來解決關於整數型頻率合成器的問題。如此可以同時達成好的頻率解析度以及較高的參考信號頻率。高的參考信號(Reference Frequency)可以允許擁有較寬的迴路頻寬,所以可以獲得較快的轉換速度(Switching Speed)與較低的相位雜訊(Phase Noise)。
本論文中利用CMOS 0.25um 1P5M 製程來實現單晶片頻率合成器並量測其特性。參考頻率設定為75MHz,除頻器的除數為32 ~ 33。壓控震盪器的輸出頻率範圍為2.4GHz ~ 2.472GHz,適用的通訊協定為IEEE 802.11b ,採用2.4GHz的ISM頻帶,
另一方面為了達到系統化降低相位雜訊之需求,兩種新的設計流程將會被介紹,分別是圖像化電路設計參數(Visualization of Design Constraints)以及新式分析相位雜訊的立體圖表。透過以上兩者的分析,可選擇最佳化的偏壓狀態以有效降低相位雜訊。此外,探討一個能夠準確預測相位雜訊的模型,這個模型將適用於手算分析以及電腦運算。上述方法都將使得設計流程更為正確以及系統化。

As wireless communication systems develop rapidly, the transceiver circuit design has been surveyed for years. In the RF front-end system, the essential component, frequency synthesizer, still needs to be further improved especially in the aspects of faster switching speed, higher operation frequency, and lower phase noise.
In this integer-based architecture, there exists laborious trade-off between the frequency resolution and the switching speed. It cannot achieve fine frequency resolution and fast switching speed at the same time. Because the bandwidth of the
loop has to be proportional to the frequency Fref, the higher the frequency resolution is, the narrower the bandwidth will be. As a result, a trade-off is inevitable between frequency resolution and loop bandwidth.Alternatively, the fractional-N frequency synthesizer is used to improve the trade-off; namely, to provide higher loop bandwidth and faster switching speed simultaneously.
As compared with the conventional technique, the operating speed of frequency synthesizer is advanced up to giga hertz in prevailing CMOS technology. Taking the advantage of today’s advanced CMOS technology, this thesis will demonstrate how to design a high-performance frequency synthesizer by using innovative techniques. The design of the 1.5V 2.4GHz frequency synthesizer in this thesis aims at the 2.4 ~2.472 GHz ISM band and is implemented in TSMC 0.25μm 1P5M CMOS technology.
In order to minimize the phase noise, two methods, namely visualization of design constraints and three-dimensional phase noise analysis diagram, are suggested to determine the optimum bias condition. Moreover, a phase noise prediction model, which is suitable for both hand calculation and computer analysis, is presented. As a result, the design process is shown to be more systematic and accurate.

1.Introduction…………………………………………1
1.1Motivation………………………………………… 1
1.2Thesis Organization…………………………… 3
2. Fundamentals of Frequency Synthesis……………… 4
2.1 Basic Principles……………………………… 4
2.2 Integer-N Frequency Synthesizer……………5
2.3 Fractional-N Frequency Synthesizer……… 6
2.4 Conclusions…………………………………… 8
3. A 1.5V 2.4GHz Fractional-N Frequency Synthesizer… 9
3.1 Introduction…………………………………………9
3.2 Phase Frequency Detector………………………10
3.3 Charge Pump and Loop Filter………………… 11
3.3.1 Charge Pump…………………………… 11
3.3.2 Loop filter…………………………… 14
3.4 Voltage-Controlled Oscillator…………… 18
3.5 Multi-Modulus Divider……………………… 21
3.6 Summary and Comparison…………………… 25
4. Graphically Optimized Method……………………… 29
4.1 Introduction……………………………………29
4.2 Phase Noise Prediction Model…………… 30
4.2.1 Brief Review of Existing Models and Definitions 30
4.2.2 Impulse Response Model for Excess Phase……32
4.2.3 Phase-to-Voltage Transformation…………… 33
4.2.4 Prediction of Phase Noise…………………… 34
4.3 Graphically Optimized Method…………………………36
4.3.1 Introduction…………………………………… 36
4.3.2 Design Process and Strategy……………… 37
A. Phase Noise Analysis…………………………… 37
B. Design Variables………………………………… 42
C. The Visualization of Design Constraints… 43
4.3.3 Experimental Results………………………… 45
4.4 Summary……………………………………… 48
5. Experimental Results…………………………… 49
5.1 The Environment of Measurement…………… 49
5.2 Experimental Results………………………… 50
5.2.1 The Experimental Results of the Building Blocks-VCO…50
5.2.2 The Experimental Results of the Building Blocks-PFD,
Charge Pump and Loop Filter……………………… 52
5.3 Summary and Discussion………………………53
6. Conclusions and Suggestions………………………… 54
6.1 Conclusions……………………………………… 54
6.2 Future Work……………………………………… 55
Appendix A……………………………………………… 56
Appendix B……………………………………………… 61
Bibliography…………………………………………… 62

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[2] Thomas H.Lee Stanford University, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998
[3] Behzad Razavi, University of California, Los Angeles, RF Microelectronics,
Prentice Hall PTR, 1998
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[5] Terrence P. Kenny, Thomas A. D. Riley, Norman M. Filiol, and Miles A. Copeland, Fellow, IEEE "Design and Realization of a Digital delta-sigma modulator for Fractional-N Frequency Synthesis" IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL.48, NO. 2, MARCH 1999, Page(s):510-521
[6] IEEE Std 802.11b — 1999 Supplement to IEEE Standard for Information Technology
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[8] "An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL's" National Semiconductor Application Note 1001 July 2001
[9] Chao-Hsin Lu, Ŗ.5Gbps Optical Transceiver Design," Master's thesis, NCU, Taiwan, R.O.C., June 2001
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[13] Jing-Yuan Zheng, "Development of CMOS Voltage-Controlled Oscillator with Quadrature Phase Output for 2.4GHz ISM Band" Master's thesis, NTHU, Hsinchu, Taiwan, MAY 2000
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[18] ElSayed, A.; Ali, A.; Elmasry, M.I. "Differential PLL for wireless applications using differential CMOS LC-VCO and differential charge pump" Low Power Electronics and Design, 1999. Proceedings 1999 International Symposium on 1999 Page(s):243-248
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[21] J. Parker et al. “A 1.6GHz CMOS PLL with On-chip loop filter” JSSC Vol 33 Mar 98
[22] J. Craninckx et al. “A Fully Integrated CMOS DCS-1800 Synthesizer” JSSC Vol 33 Dec 98
[23] A. Shahani et al. “Low Power Dividerless Frequency Synthesis” JSSC Vol 33,Dec98
[24] C. Lam et al. “A 2.6GHz/5.2GHz Frequency Synthesizer in a 0.4um CMOS Technology,” VLSI 99

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