臺灣博碩士論文加值系統

近來，2.4 -千兆赫的無線區域網路 ( WLAN ) 規格已廣泛地被市場所採用，這樣的系統支援的資料傳輸率每秒僅局限於幾兆位。然而對於能夠用很低的費用和低功率消耗以及支援每秒超過 20 個兆位元組資料傳輸率的無線區域網路系統的需求正迅速地增加。因此，在5-千兆赫的頻域中，為了滿足高速的資料傳輸需求，一些擁有超過20 個兆位元組的資料傳輸率的規格已經被制訂出來了，例如歐洲電信標準組織ETSI所制訂的HIPERLAN2規格和美國IEEE學會所制訂的802.11a規格等，這些規格提供了極誘人的即時影像、多媒體和高速視頻應用的解決方案。
在本文中，我們介紹一個整數除頻架構的頻率合成器 (integer-N frequency synthesizer) 的設計，以作為5-千兆赫的無線區域網路的應用，我們選擇HIPERLAN2作為主要的實現規格，此外我們的頻率合成器也適用於802.11a的低頻段部分。運用整數除頻架構的頻率合成器可產生符合HIPERLAN2規格的5.18-5.32千兆赫和5.5-5.7千兆赫的本地震盪頻率，可供直降式無線區域網路收發機使用。
我們利用Matlab軟體計算低通濾波器以及整個系統的參數值，利用HSPICE以及Spectre兩套軟體作電路的模擬，並以ADS軟體的行為模型(behavior model)模擬整個閉迴路系統特性。運用0.18微米的CMOS技術，我們的頻率合成器提供20兆赫的頻寬，並在1.5伏特的操作電壓下只消耗27毫瓦的耗能。在一兆赫的偏移頻率(offset frequency)下，壓控震盪器(VCO)的相位雜訊為每赫玆—109 dBc。

While wireless local area networks (WLAN) standards in the 2.4-GHz range have recently emerged in the market, the data rates supported by such systems are limited to a few megabits per second. The demand for WLAN systems that can support data rates in excess of 20 Mb/s with very low cost and low power consumption is rapidly increasing. Hence, a number of standards, such as high-performance radio LAN Type 2 (HIPERLAN2) and 802.11a, have been defined in the 5-GHz range that allow data rates greater than 20 Mb/s, offering attractive solutions for real-time imaging, multimedia, and high-speed video applications.
In this thesis, we present the design of an integer-N frequency synthesizer for 5-GHz WLAN applications. To target realistic specifications, HIPERLAN2 is chosen as the framework. Employing an integer-N architecture, the circuit generates 5.18-5.32 GHz and 5.5-5.7GHz outputs for the whole HIPERLAN2 specification. Realized in a 0.18-μm CMOS technology, the synthesizer provides a channel spacing of 20 MHz while dissipating 27 mW from a 1.5-V supply. The VCO phase noise at 1-MHz offset is equal to—109 dBc/Hz.

Contents
Abstract i
Contents ii
Figure Captions v
List of Tables viii
Chapter 1 1
1.1 Motivation 1
1.2 Summary of Research Results 3
1.3 Thesis Organization 5
Chapter 2 6
2.1 Role of the Frequency Synthesizer 6
2.2 Important Parameters in Frequency Synthesizer 7
2.2.1 Introduction 7
2.2.2 Phase Noise 7
2.2.3 Effect of Phase Noise in RF Communications 8
2.2.4 Effect of Synthesizer Sidebands in RF Communications 9
2.2.5 Lock Time of Frequency Synthesizer 10
2.3 RF Synthesizer Architectures 11
2.3.1 Introduction 11
2.3.2 Integer-N Frequency Synthesizer 11
2.3.3 Fractional-N Frequency Synthesizer 13
2.3.4 Direct Digital Frequency Synthesizer 14
2.3.5 Delay-Locked Loop Frequency multiplier 15
Chapter 3 17
3.1 Phase Frequency Detectors 17
3.1.1 Conventional three-state Phase Frequency Detector 17
3.1.2 Improved three-state PFD 19
3.2 Charge Pumps 20
3.2.1 Leakage Current 20
3.2.2 Mismatches in Charge Pump and Timing Mismatch in PFD 21
3.2.3 Charge Pump Architectures 22
3.3 Loop Filter and System Performance Considerations 24
3.3.1 PLL Linear Mathematical Model 24
3.3.2 Second Order Passive Loop Filter 25
3.3.3 Third Order Passive Loop Filter 28
3.4 Voltage-Controlled Oscillators 30
3.4.1 Oscillation mechanism 30
3.4.2 LC Tank Voltage-Controlled Oscillators 32
3.4.3 The Varactors of LC Tank VCO 34
3.4.4 Design Parameters of Complementary LC Tank VCO 36
3.5 Frequency Dividers 38
Chapter 4 40
4.1 System plan 40
4.2 Loop Parameter Design 41
4.3 VCO Design 43
4.4 PFD and Charge Pump Design 45
4.5 Frequency Divider Design 46
4.5.1 Divided-by-Two Circuit 46
4.5.2 Prescaler Circuit Design 47
4.5.2.1 Divided-by-2/3 Circuit 47
4.5.2.2 Prescaler ( Divided-by-8/9 ) circuit 50
4.5.3 Program and Swallow Counters 51
4.6 Simulation Results 53
4.6.1 System Simulation Results with MATLAB 53
4.6.2 PFD, Charge Pump and Loop Filter Simulation Results 55
4.6.3 VCO Simulation Results 57
4.6.4 Divider Simulation Results 60
4.6.5 Total Close Loop Simulation Results with behavior model 61
4.7 Summary of Simulation Results and Comparison 66
4.8 Layout 67
4.9 Measurement Result 68
4.10 Summary of Measurement Results and Discussion 71
Chapter 5 72
5.1 Conclusion 72
5.2 Future Development 73
Reference 74

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