跳到主要內容

臺灣博碩士論文加值系統

(3.238.252.196) 您好!臺灣時間:2022/08/13 23:44
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:藍國斌
研究生(外文):Kuo-Pin Lan
論文名稱:8位元,80MHz取樣頻率之CMOS脈管式類比數位轉換器
論文名稱(外文):8-bit, 80MHz Sampling Rate CMOS Pipeline Analog-to-Digital Converter
指導教授:徐永珍徐永珍引用關係
指導教授(外文):Klaus Yung-Jane Hsu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:62
中文關鍵詞:類比數位轉換器脈管式
外文關鍵詞:ADCPipeline
相關次數:
  • 被引用被引用:0
  • 點閱點閱:178
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
近年來數位電路發展迅速,諸如數位訊號處理器、中央運算處理器以及周邊晶片組,拜製程進步之賜,數位電路不只在速度上突飛猛進,在成本上也越來越低,使得數位電路在各方面的應用上越來越重要,除了原先的計算機電腦方面,在多媒體應用及無線通訊方面其比例也越來越重。
因為這樣在數位電路與週邊產品連結所需的類比數位轉換器所需傳輸速率要求也越來越高,如現今高容量的儲存裝置,就需要高傳輸速率的轉換器介面。再者,在多媒體應用方面,如 NTSC (National Television Standards Committee) 此類規格等。
尤其,最近無線通訊規格,如 802.11a,其資料頻寬亦越來越大,相對來說就需要一個高速的類比數位轉換器以符合規格。綜合上述可知高取樣頻率的類比數位轉換器是日後趨勢,方能符合資訊時代的要求。
但在日漸盛行的手提式裝置風潮下,電池的功率消耗,是必須納入考量的重要因素。而且,在成本的考量下,需以 CMOS標準製程來設計轉換器電路,除了能降低成本外,對整體電路的整合亦大有幫助。
所以,在這些條件要求下,以 CMOS 製程來設計一個高速的類比數位轉換器,但功率消耗又不會太大,以符合電子電路發展趨勢。
電路模擬的結果顯示在取樣頻率為 80MHz,輸入訊號為 38.83MHz 之正弦波時,其 SNDR 約為 43.67 dB, 且線性度表現約為 DNL 0.44LSB , 而 INL 約為 0.7LSB ,綜合上述可知,此一設計在 80MHz 的取樣頻率下成功達到有效位元約為 7 位元的表現,且線性度表現皆符合一個 LSB 的要求以內,並且達到低成本高速的類比數位轉換器的規格要求,同時又不會犧牲太多的功率消耗。

It has been proved that the digital circuit is a robust and cost effective way of signal processing over the past decade, such as digital signal processors (DSP), central processor unit (CPU), and peripheral chipsets. For this reason, the digital circuit plays a more and more important role in the information application field. In addition to the computer science application, digital circuit has become more significant in the application of the multi-media and wireless communication, such as NTSC video system and 802.11a.
As the portable devices becoming more popular, the battery power consumption is significant factor when designing the circuit. Besides, in order to reduce the cost, standard CMOS process is more suitable for the circuit design. Except for reducing the cost, it will improve the higher integration of the total system circuit.
Thus, for meeting these requirements, it’s a better choice to design the high-speed analog-to-digital converter circuit by standard CMOS process. And it can’t consume too much power for the trend of the portable device.
The objective of this research is to achieve higher transfer rate for video applications, such as camcorders and NTSC system. In order to achieve goals of low cost and high integration level, the standard digital CMOS process is employed here.
Furthermore, the circuit techniques are employed here to minimize the circuit complexity and power consumption. In other words, the better way to improve the yield and cost is to implement circuit by reducing circuit complexity. Especially, it’s very popular when the circuit is designed for applications in the future.
This thesis describes an 8-bit, 80MS/s pipeline analog-to-digital converter (ADC) implemented in 0.35 CMOS standard digital process. The ADC performance includes 0.44LSB DNL and 0.7LSB INL, 43.67 dB of SNDR for 38.83MHz input at 80MS/s. The power dissipation at 80MS/s full speed is 120mW. And the active area is around 1.8x1.5 mm2 (2.7mm2).

List of Figures iii
List of Tables vi
CHAPTER 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
CHAPTER 2 Architecture Overview 3
2.1 Overview 3
2.2 Performance Metrics and Parameters 3
2.3 Sampling Theorem 6
2.4 Non-ideal Effects on Sampling Process 7
2.4.1 Clock Jitter Error 7
2.4.2 Quantization Error 10
2.5 Evolution of Pipeline ADC Architecture 12
2.5.1 Flash ADC Architecture 12
2.5.2 Two-step ADC Architecture 14
2.5.3 Pipeline ADC Architecture 16
2.6 Power Optimization for the Pipeline ADC 18
2.6.1 Power Optimization for Each Stage 18
2.6.2 Digital Correction 21
CHAPTER 3 Circuit Techniques 25
3.1 Operational Amplifier 25
3.2 Switched Capacitor Amplifier 31
3.3 Comparator 35
3.4 Bias Circuit 36
CHAPTER 4 Prototype Implementation 40
4.1 Prototype 40
4.2 Floor Plan of the Total System 40
4.3 Floor Plan of Important Circuit Blocks 44
CHAPTER 5 Simulation Results 47
5.1 Simulation Results of Circuit Blocks 47
5.2 Simulation Results of the System 52
CHPATER 6 Conclusions and Suggestions 59
6.1 Conclusions 59
6.2 Suggestions 59
References: 60

[1] IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters, IEEE Std 1241-2000, December 2000.
[2] M. Burns and G. W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement, New York, Oxford, 2001.
[3] D. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, 1997.
[4] B. Razavi, Principles of Data Conversion System Design, New York, IEEE Press, 1995.
[5] T. B. Cho, ‘Low-Power Low-Voltage Analog-to-Digital Conversion Techniques using Pipelined Architectures’, Memorandum No. UCB/ERL M95/23, Electronics Research Laboratory, U. C. Berkeley, April 1995.
[6] http://www.mathworks.com
[7] Sedra and Smith, Microelectronic Circuits, third edition, Saunders College Publishing, 1982.
[8] N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective, second edition, Addison-Wesley, 1993.
[9] International Standard ISO/IEC 8802-11:1999 Amd 1:2000(E), IEEE Std 802.11a-1999.
[10] H. C. Yang and D. J. Allstot, ‘Considerations for Fast Settling Operational Amplifiers’, IEEE Trans. Circuits Syst. Vol. 37, No 3, pp. 326-334, March 1990.
[11] L. Dai and R. Harjani, ‘CMOS Switched-Op-Amp-Based Sample-and-Hold Circuit’, IEEE J. Solid-State Circuits, Vol. 35, No 1, pp. 109-113, Jan. 2000.
[12] Y. Park, S. Karthikeyan, F. Tsay and E. Bartolome, ‘A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8V power supply’, The 2001 IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 1,pp. 580-583, 2001.
[13] A. M. Abo and P. R. Gray, ‘A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter’, IEEE J. Solid-State Circuits, Vol. 34, No 5, pp. 599-606, May 1999.
[14] M. Yotsuyanagi, T. Etoh and K. Hirata, ‘A 10-b 50-MHz Pipelined CMOS A/D Converter with S/H’, IEEE J. Solid-State Circuits, Vol. 28, No. 3, pp. 292-300, March 1993.
[15] D. G. Nairn, ‘A 10-bit, 3V, 100MS/s Pipelined ADC’, Proceedings, Custom Integrated Circuit Conference (CICC), pp. 257-260, May 2000.
[16] M. Choi and A. A. Abidi, ‘A 6-b 1.3Gsample/s A/D Converter in 0.35-um CMOS’, IEEE J. Solid-State Circuits, Vol. 36, No. 12, pp. 1847-1858, Dec. 2001.
[17] H. Pan, M. Segami, M. Choi, J. Cao, and A. A. Abidi, ‘A 3.3-V 12-b 50-MS/s A/D Converter in 0.6-um CMOS with over 80-dB SFDR’, IEEE J. Solid-State Circuits, Vol. 35, No. 12, pp. 1769-1780, Dec. 2000.
[18] K. Y. Kim, N. Kusayanagi, and A. A. Abidi, ‘A 10-b, 100MS/s CMOS A/D Converter’, IEEE J. Solid-State Circuits, Vol. 32, No. 3, pp. 302-311, Mar. 1997.
[19] Y. Wang, and B. Razavi, ‘An 8-Bit 150-MHz CMOS A/D Converter’, IEEE J. Solid-State Circuits, Vol. 35, No. 3, pp. 308-317, Mar. 2000.
[20] L. Sumanen, M. Waltari, and K. A. I. Halonen, ‘A 10-bit 200-MS/s CMOS Parallel Pipeline A/D Converter’, IEEE J. Solid-State Circuits, Vol. 36, No. 7, pp. 1048-1055, July 2001.
[21] H. C. Choi, J. Park, S. You, H. Park, G. Kang, and J. Kim, ‘A Calibration-free 3.0V 12-BIT 20MPS A/D Converter’, The First IEEE Asia Pacific Conference on ASICs (AP-ASIC’99), pp. 190-193, 1999.
[22] S. You, K. Lee, H. C. Choi, H. Park, J. Kim, and Philip Chung, ‘A 3.3V 14-Bit 10MPS Calibration-Free CMOS Pipelined A/D Converter’, The 2000 IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 1, pp. 435-438, 2000.
[23] Y. Jeon, B. Jeon, S. C. Lee, S. Yoo, and S. H. Lee, ‘A 12b 50MHz 3.3V CMOS Acquisition Time Minimized A/D Converter’, Proceedings, Design Automation Conference, pp. 613-616, 2000.
[24] A. Pierazzi and A. Boni, ‘Design Issues for a High Frequency, 0.35um, 3.3V CMOS Folding A/D Converter’, Advanced A/D and D/A Conversion Techniques and their Applications, 27-28 July 1999 Conference Publication No. 466, IEE 1999.
[25] D. Goren, E. Shamsaev, and A. Wagner, ‘A Novel Method for Stochastic Nonlinearity Analysis of a CMOS Pipeline ADC’, Proceedings, Design Automation Conference, pp. 127-132, 2001.
[26] J. Yan, and R. L. Geiger, ‘Fast-Settling CMOS Operational Amplifiers with Negative Conductance Voltage Gain Enhancement’, The 2001 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 228-231, 2001.
[27] M. M. Amourah and R. L. Geiger, ‘Gain and Bandwidth Boosting Techniques for High-speed Operational Amplifiers’, The 2001 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 232-235, 2001.
[28] S. Cherubal, and A. Chatterjee, ‘A High-Resolution Jitter Measruement Technique Using ADC Sampling’, Proceedings, International Test Conference, pp. 838-847, 2001.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊