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研究生:蕭百珊
研究生(外文):Bae-Shan Hsiao
論文名稱:5-GHzCMOS無線區域網路之低雜訊放大器及動態匹配直接降頻式混波器
論文名稱(外文):5-GHz CMOS Low Noise Amplifier and Dynamically Matched Dirct-Downconversion Mixer for WLAN Applications
指導教授:徐永珍徐永珍引用關係
指導教授(外文):Klaus Yung-Jane Hsu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:74
中文關鍵詞:無線區域網路低雜訊放大器混波器
外文關鍵詞:WLANLNAmixer
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近年來具有高移動性的行動通訊網路設備,由於各家廠商的持續研發與投入,無線通訊技術一直維持著令人期待的遠景及發展。對於手機的普及與系統廠商附加服務的強力推展,行動通訊與網路的結合已經是勢在必行的趨勢,而且各式的產品陸續推出。其中最令人耳目一新的是無線區域網路(Wireless Local Area Network,WLAN)的推出。隨著手提電腦、PDA等相關產品熱賣,預結合行動通訊與網路,高傳輸速率的 WLAN是必要的。目前存在的無線區域網路系統大多只得是作用在2.4GHz ISM band,其所能達到最大的傳輸速率最高只達11Mbps。對於未來資訊的高承載量可能不敷使用,所以本篇論文進而研究符合HIPERLAN規格的接收器前端電路晶片設計。除低電壓、低功率消耗考量外,本論文所採用的直接移頻式接收器架構也免去了一般常使用的超外差式接受器鏡像頻道的問題,無須外接射頻鏡像移除濾波器,具較高的整合性。本篇論文所提出5-GHz 0.18mm CMOS無線區域網路之低雜訊放大器及動態匹配直接降頻式混波器。利用Spectre這套工具模擬設計所有電路。在1.5V電壓供給,此低雜訊放大器具有18dB的增益及2.6dB雜訊指數於5.4GHz頻率且具有—7.6dBmIIP3,所耗費的能量為18.8mW。而混波器部分則利用動態匹配的技術來提昇線性度且降低了1/f雜訊。動態匹配直接移頻式混波器比傳統的Gilbert cell 混波器約有20dBm IIP2的提昇且雜訊指數亦有約20dB的改善。

This paper describes a CMOS low-noise amplifier (LNA) and a mixer intended for use in Wireless Local Area Network (WLAN) front-end of direct-conversion architecture for the HIPERLAN standard. The circuits were simulated by Spectre using 0.18mm CMOS process at 1.5V supply. The LNA has a forward gain (S21) of 18dB, a noise figure (NF) of 2.6dB while draining 18.8mW at 5.4GHz frequency and —7.6dBm IIP3. The mixer makes use of dynamic matching to improve rejection of second-order intermodulation for the application within a direct-conversion receiver requiring high blocking performance. Its third order and second order input-referred intercept point (IIP3 and IIP2) are 5.2dBm and 54.8dBm, respectively. In addition, the use of dynamic matching can reduce mixer’s flicker noise. This represents 20dBm improvement over a standard Gilbert-cell mixer. The improvement of the noise floor was observed to be 30dB compared to that of a stand Gilbert-cell mixer.

1 Introduction
1.1 Motivation
1.2 Overview
2 Basic Concepts in RF Receivers Design
2.1 Receiver Architecture
2.1.1 Superheterodyne Receivers
2.1.2 Direct-Conversion or Zero-IF or Homodyne Receivers
2.1.3 Wide-Band IF Receivers
2.1.4 The Comparison Between Receiver Architecture
2.2 Performance Metrics
2.2.1 Non-linear Effect
2.2.2 Noise Figure
2.2.3 Sensitivity
2.2.4 Dynamic Range
3 Low Noise Amplifier
3.1 General considerations of LNA circuit architecture
3.1.1 Input Matching Network
3.1.2 The Design in Amplifier Circuit Diagram
3.1.3 Output Matching Network
3.2 Noise Figure Analysis of LNAs
3.2.1 Standard MOSFET Noise Model
3.2.2 Noise Figure Analysis LNAs
3.2.3 Power-Constrained Noise Optimization
3.3 Simulation Results
3.3.1 The Proposed LNA Architecture
3.3.2 Conversion between Standard and Mixed-Mode S-parameters
3.3.3 Simulation Results of LNA Circuit
3.4 Comparison between The Proposed LNA and Records
4 Mixers4.1 Common Architecture of Mixers
4.1.1 Voltage-Mixer
4.1.2 Sub-Sampling Mixer
4.1.3 Triode-Region Mixer
4.1.4 Gilbert Cell Mixer
4.2 Design of Mixer
4.2.1 Circuit Diagram of the Mixer Core
4.2.2 Dynamic Matching
4.3 Simulation Result
4.4 Comparison between The Proposed Mixer and Records
5 Conclusion

[1] G.M.Miller, “MODERN ELECTRONIC COMMUNICATION” Fifth Edition, Prentice-Hall, Inc., 1996.
[2] K.Pahlaan, A.Zahedi, and P.Krishnamurthy, “Wideband local access: Wireless LAN and wireless ATM,”IEEE commune. Mag., pp.34-40, Nov.1997.
[3] “Broadband Radio Access Networks (BRAN); high performance radio local area network (HIPERLAN) Type2; Physical (PHY) layer; functional specification,” EFSI TS 101 475 v1.1.1, April 2000.
[4] Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High-speed physical layer in the 5-GHz band, IEEE Std. 802.11a, part11, Sept. 1999.
[5] Hirad Samavati, Hamid R. Rategh, Thomas H. Lee, “A 5-GHz CMOS Wireless LAN Receiver Front End”, IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL.35, NO. 5, May. 2000,pp.769-772.
[6] Farbod Behbahani, John C. Leete, Yoji Kishigami, Asad A. Abidi, “A 2.4GHz Low-IF Receiver for Wideband WLAN in 0.6-um CMOS — Architecture and Front-End”, IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL.35, NO. 12, Dec. 2000,pp.1908-1916.
[7] Derek K. Shaeffer, Thomas H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.32, NO. 5. MAY 1997,pp.745-759.
[8] Edwin E. Bautista, Babak Bastani, and Josceph Heck, “A High IIP2 Downconversion Mixer Using Dynamic Matching” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 12, DECEMBER 2000,pp.1934-1941.
[9] P.E. Allen and D. R. Holberg, “CMOS Analog Circuit Design” Forrt Worth, TX: Holt, Finehart, and Winston, 1987, pp.490-497.
[10] S. Norsworthy et al., “Delta-Sigma Data Converters: Theory, Design, and Simulation” New York: IEEE Press, 1997, pp. 244-278.
[11] Anm-Soo Kim, Jung-Ki Choi, etc., “An Image Rejection Down Conversion Mixer Architecture”.IEEE JSSCC,Vol.31,NO.2,DEC.1972,pp321-325.
[12] Crols, J.; Steyaert, M.S.J, “A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology”, IEEE Journal of Solid-State Circuits, Volume: 30 Issue: 12 , Dec. 1995 Page(s): 1483 -1492
[13] Jan Crols and Michiel Steyaert, “CMOS Wireless Transceiver Design” Kluwer Academic Publishers, 1995.
[14] K.S.Shanmugan, “Difigital and Analog Communication Systems” New York:Wiley, 1979.
[15] B.Razavi, “Design consideration for direct-conversion receivers,” IEEE Trans. Circuits Syst. II, vol.44,pp.428-435,June 1997.
[16] S.Sampei and K. Feher,“Adaptive dc-offset compensation algorithm for burst mode operated direct-conversion receiver,” in Proc. IEEE Vehicular Technology Conf., May 1992,pp.93-96.
[17] J.F.Wilson et al., “A single-chip VHF and UHF receiver for radio paging,” IEEE J. Solid-State Circuits, vol.26, pp.1944-1950, Dec. 1991.
[18] A.Parssinen et al., “A 2-GHz wide-band direct-conversion receiver for WCDMA applications,” IEEE J. Solid-State Circuits, vol.34, pp.1893-1903, Dec. 1999.
[19] B.Lindquist et al., “A new approach to eliminate the dc offset in a TDMA direct-conversion receiver,” in Proc. IEEE Vehicular Technology, Conf., May 1993, pp.754-757
[20] Jacques C.Rudell, Jia-Jiunn Ou,Thomas Byunghak Cho, George Chien, Franceseco Brianti, “A 1.9-GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Applications” IEEE Journal of Solid-State Circuits, vol. 32, no. 12, DECEMBER 1997.
[21] Behzad Razavi, “RF Microelectronics” Prentice Hall PTR, 1998.
[22] B.Wand, J.R.Hellums, and C.G.Sodini, “MOSFET thermal noise modeling for analog integrated circuits” IEEE Journal of Solid-State Circuits,vol.29,July 1994,pp.880-889.
[23] A. van der Ziel, “Noise in Solid State Devices and Circuits” New York:Wiley,1986.
[24] “The Design of CMOS Radio-Frequency Integrated Circuits” Thomas H. Lee Published by the Press Syndicate of the University of Cambridge,1998
[25] Ting-Ping Liu, Eric Wesierwick, Nader Rohanit et,“WA 19.2 5GHz CMOS Radio Transceiver Front-end Chipset” ISSCC 2000/SESSION19/TD:High-Frequency Wireless/Paper WA 19.2
[26] Westerwick, E.H. “A 5 GHz band CMOS low noise amplifier with a 2.5 dB noise figure” VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on , 2001,Page(s): 224 -227
[27] Arvin R. Shahani, Derek K. Shaeffer, Thomas H. Lee,“ A 12mW Wide Dynamic Range CMOS Front-end for a Portable GPS Receiver,” in IEEE J. Solid-State Circuits, vol.32, no.12, Dec. 1997
[28] K.C.Hsieh et al., “A low-noise chopper-stabilized switched-capacitor filtering technique” IEEE J. Solid-State Circuits, vol. SC-18, Dec. 1983.
[29] Ting-Ping Liu, Eric Wesierwick, Nader Rohanit et, “WA 19.2 5GHz CMOS Radio Transceiver Front-end Chipset” ISSCC 2000/SESSION19/TD:High-Frequency Wireless/Paper WA 19.2
[31]Zhang, Z.; Chen, Z.; Lau “ A 900 MHz CMOS balanced harmonic mixer for direct conversion receivers”, J. Radio and Wireless Conference, 2000. RAWCON 2000. 2000 IEEE , 2000 P219 —222
[32]Pihl, J.; Christensen, K.T.; Bruun, E. “Direct downconversion with switching CMOS mixer” Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on , Vol. 1 , 2001 P117 -120
[33]P.Y.Chan, A. Rofougaran, K.A. Ahmed, and A.A.Abidi, “ A highly linear 1GHz CMOS downconversion mixer,” in Ruropean Solid-State Circuit Conference, pp.210-213, 1993.
[34]Jan Crols, and Michel S. J. Steyaert, “A 1.5GHz Highly Linear CMOS Downconversion Mixer” IEEE JSSC,VOL.30,NO.7,JULY 1995,pp.736-742.
[35]JAMEX C. SCHMOOK, “An Input Stage Transconductance Reduction Technique for High-Slew Rate Operational Amplifiers” IEEE Journal of Solid-State Circuits, vol.sc.10, NO.6, December 1975.

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