臺灣博碩士論文加值系統

近年來具有高移動性的行動通訊網路設備，由於各家廠商的持續研發與投入，無線通訊技術一直維持著令人期待的遠景及發展。對於手機的普及與系統廠商附加服務的強力推展，行動通訊與網路的結合已經是勢在必行的趨勢，而且各式的產品陸續推出。其中最令人耳目一新的是無線區域網路(Wireless Local Area Network，WLAN)的推出。隨著手提電腦、PDA等相關產品熱賣，預結合行動通訊與網路，高傳輸速率的 WLAN是必要的。目前存在的無線區域網路系統大多只得是作用在2.4GHz ISM band，其所能達到最大的傳輸速率最高只達11Mbps。對於未來資訊的高承載量可能不敷使用，所以本篇論文進而研究符合HIPERLAN規格的接收器前端電路晶片設計。除低電壓、低功率消耗考量外，本論文所採用的直接移頻式接收器架構也免去了一般常使用的超外差式接受器鏡像頻道的問題，無須外接射頻鏡像移除濾波器，具較高的整合性。本篇論文所提出5-GHz 0.18mm CMOS無線區域網路之低雜訊放大器及動態匹配直接降頻式混波器。利用Spectre這套工具模擬設計所有電路。在1.5V電壓供給，此低雜訊放大器具有18dB的增益及2.6dB雜訊指數於5.4GHz頻率且具有—7.6dBmIIP3，所耗費的能量為18.8mW。而混波器部分則利用動態匹配的技術來提昇線性度且降低了1/f雜訊。動態匹配直接移頻式混波器比傳統的Gilbert cell 混波器約有20dBm IIP2的提昇且雜訊指數亦有約20dB的改善。

This paper describes a CMOS low-noise amplifier (LNA) and a mixer intended for use in Wireless Local Area Network (WLAN) front-end of direct-conversion architecture for the HIPERLAN standard. The circuits were simulated by Spectre using 0.18mm CMOS process at 1.5V supply. The LNA has a forward gain (S21) of 18dB, a noise figure (NF) of 2.6dB while draining 18.8mW at 5.4GHz frequency and —7.6dBm IIP3. The mixer makes use of dynamic matching to improve rejection of second-order intermodulation for the application within a direct-conversion receiver requiring high blocking performance. Its third order and second order input-referred intercept point (IIP3 and IIP2) are 5.2dBm and 54.8dBm, respectively. In addition, the use of dynamic matching can reduce mixer’s flicker noise. This represents 20dBm improvement over a standard Gilbert-cell mixer. The improvement of the noise floor was observed to be 30dB compared to that of a stand Gilbert-cell mixer.

1 Introduction
1.1 Motivation
1.2 Overview
2 Basic Concepts in RF Receivers Design
2.1 Receiver Architecture
2.1.1 Superheterodyne Receivers
2.1.2 Direct-Conversion or Zero-IF or Homodyne Receivers
2.1.3 Wide-Band IF Receivers
2.1.4 The Comparison Between Receiver Architecture
2.2 Performance Metrics
2.2.1 Non-linear Effect
2.2.2 Noise Figure
2.2.3 Sensitivity
2.2.4 Dynamic Range
3 Low Noise Amplifier
3.1 General considerations of LNA circuit architecture
3.1.1 Input Matching Network
3.1.2 The Design in Amplifier Circuit Diagram
3.1.3 Output Matching Network
3.2 Noise Figure Analysis of LNAs
3.2.1 Standard MOSFET Noise Model
3.2.2 Noise Figure Analysis LNAs
3.2.3 Power-Constrained Noise Optimization
3.3 Simulation Results
3.3.1 The Proposed LNA Architecture
3.3.2 Conversion between Standard and Mixed-Mode S-parameters
3.3.3 Simulation Results of LNA Circuit
3.4 Comparison between The Proposed LNA and Records
4 Mixers4.1 Common Architecture of Mixers
4.1.1 Voltage-Mixer
4.1.2 Sub-Sampling Mixer
4.1.3 Triode-Region Mixer
4.1.4 Gilbert Cell Mixer
4.2 Design of Mixer
4.2.1 Circuit Diagram of the Mixer Core
4.2.2 Dynamic Matching
4.3 Simulation Result
4.4 Comparison between The Proposed Mixer and Records
5 Conclusion

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