臺灣博碩士論文加值系統

在CMOS製程技術的成熟以及元件尺寸不斷縮小，利用CMOS設計的高頻電路已可達到系統所需求的效能，這使得CMOS高頻元件越來越受到重視。但隨著CMOS製程尺寸的縮小，閘極氧化層越來越薄，使得氧化層可靠度下降；MOS元件通道長度越來越短，汲極源極的參雜濃度必須增加以有效防止通道的punch-through，伴隨之而來的卻是MOS元件因淺接面的形成而導致對ESD的防護能力下降。這些先進製程卻留下一個最大的不良後遺症，就是用這些先進製程製作的CMOS IC很容易就被ESD所破壞，造成CMOS IC的可靠度問題。ESD防護電路是積體電路上專門用來做靜電放電防護之用的特殊電路，此靜電放電防護電路提供了ESD電流路徑，以免ESD放電時電流流入IC內部電路而造成損傷。隨著製程微小化的演進，部分先進製程雖然有助於提升IC的性能使其可應用於高頻，但卻也付出了ESD防護能力的下降。因此，如何在先進製程技術中，尋求提供有效的全晶片ESD防護是本論文所探討的重點。
在本論文中對高頻的ESD靜電防護技術作深入之探討。除了採以電感來當作信號輸入端的ESD防護元件來減低輸入端的負載效應bypass ESD的大電流外，在本論文的前半段更提出一個在CMOS製程技術中，不需增加額外的光罩或製程步驟，即可大幅降低佈局面積，可提供壓艙電阻(ballasting resistance)的創新島嶼型汲極NMOS電晶體，達到所需的ESD測試標準。此島嶼結構在Salicide製程下利用島嶼狀改變電流在NMOS汲極擴散區之行進路徑以增加汲極壓艙電阻，因此促使GGNMOS電晶體能更均勻地導通。而島嶼型汲極結構除了增加壓艙電阻外，尚增加了產生碰撞解離電流的面積，形成pseudo collector效應。在諸多效應下，島嶼型結構MOS電晶體的ESD防護能力亦確有明顯增加，可降低佈局面積達到需求的ESD測試標準。

In order to ensure IC products can go to the market smoothly and on time, function faultless and reliability are very important. But as we know, the key point is if they can pass ESD testing or not. Although some advanced processes help prompting IC performance with processes scaling down, it pays the expense of reducing ESD performance also. How to invent novel devices or circuits to provide a whole chip ESD protection in deep sub-micron technology is the main point in this thesis.
In this thesis, a new ESD protection methodology for high frequency CMOS RF LNAs is in realized. An on-chip inductor is employed to drain off the hazardous ESD charge while tuning out the harmful parasitic input capacitance. Besides that, we propose the islanded drain NMOS transistor for ESD protection. Without any additional process steps and mask numbers, the novel structure utilizes islands to change current path in NMOS drain diffusion region to increase drain ballast resistance in salicide process. So it can promote GGNMOS transistor turn on more uniformly. In addition to increasing ballast resistance, the island structure also increases the area of impact ionization current. In aspect of simulation and experiment, it proves the structure indeed improving ESD protection ability of devices. ESD performance of the novel structure indeed apparently be improved under such a lot of effects. Moreover, the islanded drain structure also can substantially reduce layout area to achieve ESD testing requirement.

目錄
第一章 緒論 1
1-1研究動機與目的 1
1-2論文架構 3
第二章 ESD防護之研究 4
2-1 ESD測試模式 5
2-2常用ESD防護元件或電路之研究 8
2-2-1 二極體 9
2-2-2閘極接地之金氧半N型電晶體 10
2-2-3閘極耦合N型金氧半電晶體 15
第三章 創新島嶼型汲極MOS電晶體之研究 15
3-1創新島嶼型汲極MOS電晶體之壓艙電阻效應 19
3-2創新島嶼型汲極MOS電晶體之抑制汲極接面軟性崩潰效應 23
3-3一般製程中創新島嶼型汲極MOS電晶體之實現 29
第四章 創新島嶼型汲極電晶體之實驗結果與討論 31
4-1島嶼型元件之ESD防護能力 32
4-2島嶼型元件之驅動能力 38
4-3島嶼型元件之可靠性量測分析 43
第五章 RF(Giga-Hz)高頻電路之ESD防護設計 48
5-1 RF積體電路的ESD保護元件考量 49
5-2低雜訊放大器及其ESD保護電路設計架構 52
5-3低雜訊放大器電路模擬結果 55
5-4島嶼型元件之ESD保護電路模擬結果 59
5-5 ESD防護設計量測結果與討論 61 第六章 結論 64
參考文獻

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