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研究生:廖于慧
研究生(外文):Yu-Hui Liao
論文名稱:100MHz8位元之全差動取樣與保持電路
論文名稱(外文):An 8-bit 100MHz Fully Differential Sample-and-Hold Circuit
指導教授:連振炘
指導教授(外文):Chenhsin Lien
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
中文關鍵詞:取樣與保持
外文關鍵詞:Sample-and-HoldData Converter Circuits
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本篇論文呈現一TSMC 0.18 CMOS製程取樣保持與電路的模擬結果。此取樣與保持電路由高速運算放大器、電容、NMOS電晶體開關及高輸出電壓產生器構成,此外亦包含一由NAND組成的nonoverlap時脈產生器。
本電路所使用的高速運算放大器為折疊疊串的架構。在1.8伏的操作電壓,2p的負載下有55.9dB的增益,及515MHz(約五倍取樣頻率)的單一增益頻寬。為了得到較高的精確度,此一取樣與保持電路採用相關雙重取樣的結構,以消除電壓偏移及增益誤差而提高線性度,且利用bottom-plate sampling的技巧,使電晶體開關在關掉時注入汲極或源極的電荷固定,再利用全差動的架構,消除MOS開關在切換時因注入電荷所造成的誤差。全差動使得整個電路對雜訊有較高的免疫力,但需要一個共模回授電路以固定輸出的直流電壓,避免運算放大器偏離工作區間而造成錯誤。在此論文中,我們採用切換電容式的共模回授電路來達到此要求。切換電容式的共模回授電路比起連續時間共模回授電路的主要優點即有較大的輸出範圍,這點在低操作電壓的情況下特別有用。此外,我們採用高輸出電壓產生器,使得MOS電晶體開關能達到所需的線性度,並可以NMOS電晶體開關取代有較高動態範圍的CMOS開關,化簡電路的時脈及線路。
此一取樣與保持電路在100MHz的取樣頻率下,可達八位元的解析度,且在1Vpp的輸入信號下有25MHz的頻寬。在1.8伏的操作電壓下,整個電路消耗的功率為34mW。

This thesis describes a 100MHz, 8-bit resolution CMOS fully differential sample-and-hold circuit under 1.8V operation voltage. The circuit is composed of a high-speed operational amplifier, capacitors, MOS transistor switches, and a high voltage generator.
The fully differential folded cascode structure is used in the design of high-speed operational amplifier. A DC gain of 55.9dB, and an unity gain frequency of 515MHz with 2p load capacitors, are obtained. The sample-and-hold circuit uses the correlated-double-sampling structure to reduce the offset voltage, gain error, and noises. A high voltage generator circuit is used to boost the clock to obtain better linearity.
This circuit achieves 8-bit resolution when operating at 100MHz clock rate with 1 Vpp input signal, and the input signal bandwidth is up to 25MHz. The total power consumption is 34mW.

CHAPTER 1 Introduction 1
1.1 Introductions and Motivation 1
1.2 Thesis Organization 2
CHAPTER 2 Fundamental of Sample and Hold Circuits 3
2.1 Introduction 3
2.2 Introduction to the S/H Circuit and Deficiency 4
2.3 Architecture Analyses of the Sample-and-Hold circuits 9
2.3.1 Conventional open-loop architecture 9
2.3.2 Conventional Close-Loop Architecture 10
2.4 Considerations of the S/H Circuit 12
2.3.1 S/H with Correlated Double Sampling (CDS) 12
2.5 The Proposed S/H circuit with CDS 15
CHAPTER 3 The Operational Amplifier 19
3.1 Introduction 19
3.2 Design Considerations of the Fully Differential Op Amp 20
3.3 Circuit Fulfillment 25
3.3.1 The Folded Cascode Op Amp 25
3.3.2 Common Mode Feedback (CMFB) Circuits 26
3.3.3 Wide-Swing Constant-Transconductance Bias Circuit 27
3.3.3.1 Wide-Swing Current Mirrors 27
3.3.3.2 Wide-Swing Constant-Transconductance Bias Circuit 29
CHAPTER 4 Detailed Discussions and Simulation Results 32
4.1 Introduction 32
4.2 The Capacitors and MOST Switches 33
4.2.1 Capacitors 33
4.2.2 Low Voltage Operations of Switched-Capacitor Circuits 35
4.2.3 The MOST Switch 36
4.2.4 The Clock generator 39
4.3 Simulation Results 41
CHAPTER 5 The Conclusion and the Future Perspective 44
5.1 Conclusion 44
5.2 The Future Perspective 44
Appendix
Bibliography

[1] David A. Johns and Ken Martin, “Analog Integrated Circuit Design”, John Wiley and Sons, Inc., 1997.
[2] Thomas Byunghak Cho, Paul R. Gray, “A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter”, IEEE Journal of Solid-State Circuits, vol.30, pp. 166-172, Mar. 1995.
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