臺灣博碩士論文加值系統

本實驗中，我們成功地製作了N通道的金屬（Al）/氧化鉿（HfO2）/半導體（p-Si）的場效電晶體，我們使用射頻磁控濺鍍法沈積HfO2薄膜，在基本電性上的表現，如：ID-VD，ID-VG及C-V等，皆證明電晶體能夠正常的操作，且發現臨界電壓的範圍約在0.67~0.83V，最小的次臨界斜率是78.5 mV/dec.，在VD=0.05V下，ION/IOFF的比例有6個數量級之多，顯示電晶體有非常好的電流切換能力。經由次臨界斜率St=2.3(kT/q)[1+(CD+Cit)/Cox]的計算，可以得到界面缺陷電荷密度（Dit）約為3.16x1012 cm-2-(eV)-1。
接下來，我們也製備金屬（Au）/氧化鉿（HfO2）/半導體（p-Si）MIS（Metal-Insulator-Semiconductor）結構的電容器，並對元件作基本的變溫電性量測，溫度範圍在300 K至425 K，所得到的結果顯示在低電場（＜0.8MV/cm）下，Au/HfO2界面間的電流傳導機制為蕭基發射所主導，在-1V的偏壓下漏電流為-6.5×10-3A/cm2，介電常數為18.9，HfO2薄膜的厚度為133.4 nm。至於材料物性方面，我們也作了SIMS、XRD及SEM等分析，亦有了些許的收穫，晶粒大小為20 nm，快速熱退火處理後，並不影響HfO2薄膜的結構及性質。
經由閘控二極體的量測，我們亦得到的一些結果，分別如下：界面缺陷電荷密度5.3x1013 cm-2-eV-1，表面復合速率4310 cm/s，少數載子生命週期 2.2x10-8 sec，經由和傳統SiO2電晶體與學長的Ta2O5電晶體作一比較，發現電晶體特性及相關參數沒有傳統SiO2電晶體好，但由於熱穩定性較Ta2O5好，所以HfO2非常適合當作下一代電晶體的閘極氧化層材料。

N-channel metal-oxide-semiconductor field effect transistors (MOSFETs) using HfO2 gate oxide were fabricated successfully. The HfO2 films were deposited by RF magnetron sputtering. The C-V, ID-VD and ID—VG characteristics are measured. The minimum threshold voltage was 0.67 V. The minimum subthreshold swing was 78.5 mV/dec. The ION/IOFF ratio is about 106 at VD=0.05 V, which indicates that the HfO2 MOSFETs have good current switch capability. Since St=2.3(kT/q)[1+(CD+Cit)/Cox], the interface trapped charge density Dit is extracted to be about 3.16x1012 cm-2-eV-1. The dielectric constant measured from a separate metal-HfO2-silicon capacitor is 18.9.
Au/HfO2/p-Si metal-insulator-silicon (MIS) capacitors were also fabricated to characterize the electrical properties of the HfO2 dielectric. The electrical conduction mechanisms of HfO2 thin film as functions of temperature were studied. The temperature range is from 300 to 425 K. The leakage current density is -6.5×10-3A/cm2 when the applied voltage is -1 V and the HfO2 thickness is 133.4 nm. At low electrical field (<0.8 MV/cm) and with the Au electrode biased negative, the conduction mechanism of Au/HfO2 interface is Schottky Emission. The SIMS, XRD and SEM analyses were made.
The interface trapped charge density, the surface recombination velocity, and the minority carrier lifetime in the field-induced depletion region measured from gated diodes were 5.3x1013 cm-2-eV-1, 4310 cm/s, and 2.2x10-8 sec, respectively. A comparison with MOSFETs using SiO2 and Ta2O5 gate oxides was made. The HfO2/Si interface is generally inferior compared with that of the SiO2/Si interface. But the HfO2/Si interface is comparable to that of the Ta2O5/Si interface. The thermodynamic stability of HfO2 gate oxide is much better than that of Ta2O5 date oxide. In the future, MOSFETs with HfO2 gate oxide will be a promising candidate for sub-0.1 um MOSFETs.

第一章 緒論
1.1 高介電常數（High-κ）薄膜於極大型積體電路（ULSI）的發展
1.2 High-κ薄膜在DRAM上的應用
1.3 HfO2薄膜的製備方法
1.4 High-κ薄膜於MOSFET閘極氧化層（Gate Oxide）的發展
1.5 本論文的研究方向
第二章 熱穩定性（Thermodynamic Stability）之探討
2.1 「熱穩定性」理論簡介
2.2 矽化物（Silicide）及矽酸鹽（Silicate）的產生
2.3 其他相關文獻
第三章 HfO2（氧化鉿）薄膜元件的製備
3.1 射頻磁控濺鍍法（RF Magnetron Sputtering）的簡介
3.2 歐姆接面（Ohmic contact）的製備
3.3 HfO2薄膜的成長
3.4 HfO2薄膜電容器的製備
3.5 HfO2薄膜電晶體的製備
3.6 量測儀器以及實驗儀器介紹
3.7 蝕刻上遭遇到的問題
第四章 HfO2薄膜基本介紹及物性量測分析
4.1 HfO2薄膜的基本介紹
4.2 二次離子質譜儀（SIMS）縱深分佈之分析
4.3 X-Ray 繞射分析
4.4 掃瞄式電子顯微鏡（SEM）照相分析
第五章 Au/HfO2/Silicon電容器基本電性及漏電流機制分析---21
5.1 I-V（電流-電壓）特性曲線量測
5.2 C-V(電容-電壓)特性曲線量測
5.3 漏電流傳導機制之簡介
5.3.1 蕭基發射（Schottky emission
5.3.2 普爾-法蘭克發射（Poole-Frenkel Emission
5.3.3 傅勒-諾德翰穿隧（Fowler-Nordheim Tunneling
5.3.4 跳躍傳導（Ohmic Conduction，Hopping Conduction
5.4 MIS結構電容器與溫度變化之漏電流傳導機制分析
5.5 本章結論
第六章 Al/HfO2/Silicon場效電晶體基本電性量測
6.1 IDS-VDS Curve的特性探討
6.2 IDS-VGS Curve的特性探討
6.3 次臨界斜率（Sub-threshold Swing）
6.4 臨界電壓（VT）的粹取
6.5 遷移率（Mobility）的探討
6.6 基板效應（Body Effect）
6.7 漏電流傳導機制
6.8 閘控二極體（Gated-Diode）量測
6.8.1閘控二極體量測方法與介紹
6.8.2閘控二極體量測理論跟線路接法
6.8.3閘控二極體量測參數探討
第七章 結論
Reference
Experimental Diagrams and Tables
Appendix
A. 電晶體製程之三道光罩圖
B. HfO2之相圖（Phase Diagram）
C. Operation of the Samco PD-10TA PECVD Machine
D. HfO2 Transistor Paper Research
MOSFET製程條件一覽表

[1] H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Makamura, M. Saito, and H. Iwai, “1.5 nm direct-tunneling gate oxide Si MOSFET’s,” IEEE Trans. Electron Devices, vol. 43, pp. 1233—1241, August 1996.
[2] J. L. Autran, R. Devine, C. Chaneliere, and B. Balland, “Fabrication and characterization of Si-MOSFET’s with PECVD amorphous Ta2O5 gate insulator,” IEEE Electron Device Lett., vol. 18, pp. 447—449, September 1997.
[3] C. Chaneliere, S. Four, J. L. Autran, R. A. B. Devine, and N. P. Sandler, “Properties of amorphous and crystalline Ta2O5 thin films deposited on Si from Ta(OC2H5)5 precursor,” J. Appl. Phys., vol. 83, no. 9, pp. 4823-4829, May 1998.
[4] Q. Lu, D. Park, A. Kalnitsky, C. Chang, C. C. Cheng, S. P. Tay, T. J. King, and C. Hu, “Leakage Current Comparison Between Ultra-Thin Ta2O5 Films and Conventional Gate Dielectrics,” IEEE Electron Device Lett., vol. 19, no. 9, pp. 341-342, September 1998.
[5] D. Park, Y. King, Q. Lu, T. J. King, C. Hu, A. Kalnitsky, S. P. Tay, and C. C. Cheng, “Transistor Characterization with Ta2O5 Gate Dielectric,” IEEE Electron Device Lett., vol. 19, no. 11, pp. 441-443, November 1998.
[6] B. C. Lai, N. Kung, and J. Y. Lee, “A study on the capacitance-voltage characteristics of metal-Ta2O5-silicon capacitors for very large scale integration metal-oxide-semiconductor gate oxide applications,” J. Appl. Phys., vol. 85, no. 8, pp. 4087-4090, April 1999.
[7] J. C. Yu, B. C. Lai, and J. Y. Lee, “Fabrication and Characterization of Metal-Oxide-Semiconductor Field-Effect Transistors and Gated Diodes Using Ta2O5 Gate Oxide,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 537-539, November 2000.
[8] B. C. Lai, J. C. Yu, and J. Y. Lee, “Ta2O5/Silicon Barrier Height Measured from MOSFETs Fabrication with Ta2O5 Gated Dielectric,” IEEE Electron Device Lett., vol. 22, no. 5, pp. 221-223, May 2001.
[9] B. Cheng et al., “The Impact of High-K Gate Dielectrics and Metal Gate Electrodes on Sub-100 nm MOSFET’s,” IEEE Transactions on Electron Devices, vol. 46, no. 7, pp. 1537-1544, July 1999.
[10] B. H. Lee et al., “Ultrathin Hafnium Oxide with Low Leakage and Excellent Reliability for Alternative Gated Dielectric Application,” IEDM Tech. Dig., pp. 133-136, 1999.
[11] G. D. Wilk, and R. M. Wallace, “Electrical properties of hafnium silicate gate dielectrics deposited directly on silicon,” Appl. Phys. Lett., vol. 74, no. 19, pp. 2854-2856, May 1999.
[12] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “Hafnium and zirconium silicates for advance gate dielectrics,” J. Appl. Phys., vol. 87, no. 1, pp. 484-492, January 2000.
[13] B. H. Lee, L. Kang, R. Nieh, W. J. Qi, and J. C. Lee, “Thermal stability and electrical characteristics of ultrathin hafnium oxide gate dielectric reoxidized with rapid thermal annealing,” Appl. Phys. Lett., vol. 76, no. 14, pp. 1926-1928, April 2000.
[14] L. Kang, B. H. Lee, W. J. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi, and J. C. Lee, “Electrical Characteristics of Highly Reliable Ultrathin Hafnium Oxide Gate Dielectric,” IEEE Electron Device Lett., vol. 21, no. 4, pp. 181-183, April 2000.
[15] S. Lee et al., “High Quality Ultra Thin CVD HfO2 Gate Stack with Poly-Si Gate Electrode,” IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 31-34, 2000.
[16] L. Kang, Y. Jeon, K. Onishi, B. H. Lee, W. J. Qi, R. Nieh, S. Gopalan, and J. C. Lee, “Single-layer Thin HfO2 Gate Dielectric with n+-Polysilicon Gate,” IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 44-45, 2000.
[17] L. Kanget al., “MOSFET Device with Polysilicon on Single-Layer HfO2 high-K Dielectrics,” IEDM Tech. Dig., pp. 35-38, 2000.
[18] B.H. Lee et al., “Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8A-12A),” IEDM Tech. Dig., pp. 39-42, 2000.
[19] H. Lee, S. Jeon, and H. Hwang, “Electrical characteristics of a Dy-doped HfO2 gate dielectric,” Appl. Phys. Lett., vol. 79, no. 16, pp. 2615-2617, October 2001.
[20] D. A. Neumayer, and E. Cariter, “Materials characterization of ZrO2-SiO2 and HfO2-SiO2 binary oxides deposited by chemical solution deposition,” J. Appl. Phys., vol. 90, no. 4, pp. 1801-1808, August 2001.
[21] A. Callegari, E. Cariter, H. F. Okorn-Schmidt, and T. Zabel, “Physical and electrical characterization of Hafnium oxide and Hafnium silicate sputtered films,” J. Appl. Phys., vol. 90, no. 12, pp. 6466-6475, December 2001.
[22] T. Ma, et al., “Group IVB Metal Oxide High Permittivity Gate Insulators Deposited From Anhydrous Metal Nitrates,” IEEE Transactions on Electron Devices, vol. 48, no. 10, pp. 2348-2356, October 2001.
[23] K. Onishi et al., “Dopant Penetration Effects on Polysilicon Gate HfO2 MOSFET’s,” IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 131-132, 2001.
[24] S. J. Lee et al., “Performance and Reliability of Ultra Thin CVD HfO2 Gate Dielectrics with Dual Poly-Si Gate Electrodes,” IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 133-134, 2001.
[25] R. Choi et al., “High-Quality Ultra-thin HfO2 Gate Dielectric MOSFETs with TaN Electrode and Nitridation Surface Preparation,” IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 15-16, 2001.
[26] Y. Kim et al., “Conventional n-channel MOSFET device using single layer HfO2 and ZrO2 as high-k gate dielectrics with polysilicon gate electrode,” IEDM Tech. Dig., pp. 455-458, 2001.
[27] W. Zhu et al., “HfO2 and HfAlO for CMOS: Thermal Stability and Current Transport,” IEDM Tech. Dig., pp. 463-466, 2001.
[28] C. Hobbs et al., “80nm Poly-Si Gate CMOS with HfO2 Gate Dielectric,” IEDM Tech. Dig., pp. 651-654, 2001.
[29] H. —J. Cho et al., “Novel Nitrogen Profile Engineering for Improved TaN/HfO2/Si MOSFET Performance,” IEDM Tech. Dig., pp. 655-658, 2001.
[30] K. Onishi et al., “Reliability Characteristics, Including NBTI, of Polysilicon Gate HfO2 MOSFET’s,” IEDM Tech. Dig., pp. 659-662, 2001.
[31] M. Gutowski, J. E. Jaffe, C. L. Liu, M. Stoker, R. I. Hegde, R. S. Rai, and P. J. Tobin, “Thermodynamic stability of high-K dielectric metal oxide ZrO2 and HfO2 in contact with Si and SiO2,” Appl. Phys. Lett., vol. 80, no. 11, pp. 1897-1899, March 2002.
[32] B. K. Park, J. Park, M. Cho, C. S. Hwang, K. Oh, Y. Han, and D. Y. Yang, “Interfacial reaction between chemically vapor-deposited HfO2 thin films and a HF-cleaned Si substrate during film growth and postannealing,” Appl. Phys. Lett., vol. 80, no. 13, pp.2368-2370, April 2002.
[33] P.D. Kirsch, C.S. Kang, J. Lozano, J. C. Lee, and J. G. Ekerdt, “Electrical and spectroscopic comparison of HfO2/Si interfaces on nitrided and un-nitrided Si (100),” J. Appl. Phys., vol. 91, no. 7, pp. 4353-4363, April 2002.
[34] Joseph Ya-min Lee and Benjamin Chihming Lai, Handbook of Thin Films Material, edited by H. S. Nalwa, vol. 3: Ferroelectric and Dielectric Thin Films.
[35] W. J. Zhu, T. P. Ma, T. Tamagawa, J. Kim, and Y. Di, “Current Transport in Metal/Hafnium Oxide/Silicon Structure,” IEEE Electron Device Lett., vol. 23, no. 2, pp. 97-99, February 2002.
[36] K. J. Hubbard and D. G. Schlom, “Thermodynamic stability of binary oxides in contact with silicon,” J. Mater. Res., vol. 11, no. 11, pp. 2757—2776, 1996.
[37] M.Balog, M.Schieber, M.Michman, and S.Patai, “Chemical Vapor Deposition and Characterization of HfO2 Films From Organo-Hafnium Compounds,” Thin Solid Films, vol. 41, pp. 247- 259, August 1997.
[38] S. M. Sze, Physics of Semiconductor Device, 2nd ed., Wiley, New York, 1981.
[39] D. K. Schroder, Semiconductor Material and Device Characteristics, Wiley, Arizona, 1998.
[40] MRS BULLETIN, Alternative Gate Dielectrics for Microelectronics, vol. 27, no. 3, March 2002.
[41] Ernest M. Levin, Carl R. Robbins and Howard F. McMurdie; Margie K. Reser, editor, Phase diagrams for ceramists, American Ceramic Society, 1974.
[42] Note, “MOSFET Carrier Mobility Model Based on Gate Oxide Thickness, Threshold Voltage and Gate Voltages,” Solid-State Electronics vol. 39, no. 10, pp. 1515-1518, 1996.
[43] Sorin Cristoloveanu, Hisham Haddara, and Nathalie Revil, “Defect Localization Induced by Hot Carrier Injection in Short Channel MOSFETs: Concept, Modeling, and Characterization,” Microelectro. Reliab. , vol. 33, no. 9, pp. 1365-1385, 1993.
[44] A. S. Grove And D. J. Fitzgerald, “Surface Effects on p-n Junctions: Characteristics of Surface Space-Charge Regions Under non-Equilibrium Conditions ,” Solid-Electronics Pergamon press, vol. 9, pp. 783-806. 1966.
[45] P. U. Calzolari And S. Graffi, “A Theoretical Investigation on The Gernation Current In Silicon p-n Junctions Under Reverse Bias,” Solid-State Electronics, vol.15, pp. 1003-1011, 1972.
[46] T. Giebel and K. Goser, “Hot-Carrier Degradation of n-Channel MOSFET’s Characterized by a Gated-Diode Measurement Technique,” IEEE Electron Device Lett., vol. 10, no. 2, pp. 76-78, February 1989.
[47] P. C. T. Roberts And J. D. E. Beynon, “An Experimental Determination Of The Carrier Lifetime Near The Si-SiO2 Interface,” Solid-State Electronics, Vol.16, pp. 221-227, 1973.
[48] 賴志明，應用於金氧半電晶體閘極氧化層的氧化鉭薄膜電性之研究，國立清華大學博士論文，民國九十年六月。
[49] 余錦旗，金屬/氧化鉭/半導體場效電晶體的試製與電性分析，國立清華大學碩士論文，民國八十八年六月。