|
References [1] M. D. Ker , ”Electrostatic discharge protection circuits in CMOS ICs using the lateral SCR devices: an overview,” Electronics, Circuits and Systems, 1998 IEEE International Conference on , Vol. 1 , 1998, Page(s): 325 -328 vol.1. [2] S. H. Voldman and V. P. Gross, “Scaling, Optimization And Design Considerations Of Electrostatic Discharge Protection Circuits In CMOS Technology,” EOS/ESD, Symp., Proc., pp. 251-260, 1993. [3] C. Duvvury and A. Amerasekera, “ESD: a pervasive reliability concern for IC technologies,” Proceedings of the IEEE , Volume: 81 Issue: 5 , May 1993 pp. 690 —702. [4] P. K Chatterjee, W. R. Hunter, A. Amerasekera, S. Aur, C. Duvvury, P. E. Nicollian, L. M Ting, P. Yang , ”Trends for deep submicron VLSI and their implications for reliability,” in Reliability Phy., Sympo., 33rd Annual Proc., IEEE International, pp. 1-11, 1995 . [5] A. Amerasekera and C. Duvvury, “ ESD in Silicon Integrated Circuits“, John Wiley & Sons,Chap-3 PP 49 ~ 52, 1994. [6] A. Amerasekera and C. Duvvury, “The Impact of technology scaling on ESD roubustness and protection circuit design,” in 1994 EOS/ESD Symp. Proc., Vol. EOS-16, pp. 237-245. [7] S. Daniel and G. Krieger, “ Process and design optimization for advanced CMOS I/O ESD protection devices “, EOS/ESD Symp. Proc., EOS-12, pp.206-213, 1990. [8] G. Notermans, A. Heringa, V. Dort, S. Jansen and F. Kuper “The effect of silicide on ESD performance,“ IRPS 1999, pp. 154 —158. [9] D. K. Davies, “The ESD threat,“ in Electrical Overstress/Electrostatic Discharge Symposium, 1996. Proceedings , 1996 Page(s): 322 —326. [10] A. Chatterjee, T. Polgreen , “ A Low-Voltage Triggering SCR For On-Chip ESD Protection at Output And Input Pads”,1990 Symposium on VLSI Technology,6B-5.1990. [11] S. K. Ghandhi, “Semiconductor Power Device”, New York: Wiley, 1977. [12] A. Amerasekera,; M,-C. Chang,.; J. Seitchik, A. Chatterjee,K. Mayaram, J.-H. Chern, “ Self-heating effects in basic semiconductor structures ”, IEEE Trans. Elec. Dev., ED-40, p.1836-1844,1993. [13] I. Son, T.-W. Tang and D.H. Navon, “Modeling of bistable device I-V characteristic resulting from conductivity modulation in semiconductors,” in Electron Devices, IEEE Transactions on , Vol. 35 Issue: 4 Part: 2, pp. 450 —458, April 1988. [14] G. Krieger and P. Niles, “Diffused resistors characteristics at high current density levels-analysis and applications,” in IEEE Trans. Elec. Dev., Vol.36, p. 416-423,1989. [15] P. L. Hower, V. G. K. Reddi, “Avalanche Injection and Second Breakdown in Transistor”, IEEE Trans. Elec. Dev., ED-17, p. 320-335,1970. [16] B. S. Khurana, T. Sugano, H. Yanai, “Thermal Breakdown in Silicon p-n Junction Devices”, IEEE Trans. Elec. Dev., ED-13, p. 763-770,1966. [17] N. R. Howard and G. W. Johnson, “P+-I-N+ Silicon Diodes at High Forward Current Densities”, Solid State Electronics, Vol. 8. 1965, pp. 275-284. [18] D. L. Pulfrey and N. G. Tarr, “Introduction to Microelectronic Devices”, Prentice-Hall International. Inc., 1989. [19] A. Chatterjee, J. A. Seitchik, J.-H. Chern, P. Yang, C.-C. Wei, “Direct evidence supporting the premises of a two-dimensional diode model for the parasitic thyristor in CMOS circuits built on thin epi,” IEEE Electron Device Letters , Vol. 9 Issue: 10, pp.509 —511, Oct. 1988. [20] G. Krieger, “The Dynamics of Electrostatic Discharge Prior to Bipolar Action Related Snapback”, in Proc. 11th EOS/ESD Symposium, pp.136-144, 1989. [21] S. M. Sze, “ Physics of Semiconductor Devices “, 2nd edn, John Wiley & Sons, 1981, [22] M. Reisch, “ On bistable behavior and open-base breakdown of bipolar transistors in the avalanche regime-modeling and applications “ Electron Devices, IEEE Transactions on , Volume: 39 Issue: p 1398 -1409, 1992 . [23] R. W. Dutton, “Bipolar Transistor Modeling of Avalanche Generation for Computer Circuit Simulation”, IEEE Trans. Elec. Dev., ED-22, pp.334-338, 1975. [24] C. Fiegna, L. Selmi, E. Sangiorgi, B. Ricco, “Three-dimensional effects in dynamically triggered CMOS latchup ,“ in Electron Devices, IEEE Transactions on , Vol. 36 Issue. 9 Part: 2 , pp.1683 —1690, Sept. 1989. [25] J. Y. Chen, “ CMOS Devices And Technology For VLSI “, Prentice-Hall International,Inc., Chap-8 PP 285~320,1990. [26] D. L. Lin, “ESD Sensitivity And VLSI Technology Trends: Thermal Breakdown And Dielectric Breakdown,” EOS/ESD Symp., Proc., 1993, pp. 73 —81 [27] C. Diaz, Kang, S. M, C. Duvvury, “Electrical overstress and electrostatic discharge ,” in Reliability, IEEE Trans., Vol. 44 Issue: 1, pp.2 —5, 1995. [28] S. Dabral, T. Maloney, “Basic ESD and I/O Design”, Intel Corp. Wiley, 1998. [29] 柯明道,吳添祥, “ 次微米戶互補式金氧半積體電路之靜電放電防護_進階篇 ”, 電 腦與通訊期刊(CCL Technical Journal),第84期,第84~96頁, 1996年九月. [30] 柯明道,吳添祥, “ 次微米戶互補式金氧半積體電路之靜電放電防護_概念教導”, 電 腦與通訊期刊(CCL Technical Journal),第42期,第10~42頁, 1995年九月. [31] “Electrostatic Discharge(ESD) Sensitivity Testing Human Bodt Model(HBM)-JESD22-A114-B”, in JEDEC Standard, Jun, 2002. [32] “Electrostatic Discharge(ESD) Sensitivity Machine Model(HBM)-EIAJESD22-A115-A”, in JEDEC Standard, Oct., 1997. [33] “Field-Induced Charged-Device Model Test Methode for Electrostatic Discharge — Withstand Thresholds of Microelectronic Components — JESD22-C101-A”, in JEDEC Standard, Jun., 2000. [34] C. Duvvury, A. Amerasekera, “Advanced CMOS protection device trigger mechanisms during CDM, “ in EOS/ESD Symp., Proc., pp. 162-174 , 1995. [35] MIL-STD-883C method 3015.7, "Military Standard Test Methods and Proc. For Microelectronics", Dept. of Defense, Washington, D. C., U.S.A., 1989. [36] J.-C. Lee, R. Young, J. J. Liou, G.D. Croft, and J. C. Bernier, “An Improved Expwrimental Setup for Electrostatic Discharge (ESD) Measurements Based on Transmission Line Pulsing Technique,” IEEE Trans. Device and Material Reliability, Vol. 50, No. 6, Dec. 2001. [37] H. Hyatt, J. Harris, A. Alonzo, P. Bellew, “TLP Measurement for Verification of ESD Protection Device Response,” IEEE Trans. Device and Material Reliability, Vol. 24, No. 2, Apr. 2001. [38] P. A. Juliano, E. Rosenbaum, “Accurate Wafer-Level [39] J. Barth, J. Richner, and K. Verhaege, “TLP calibration, correlation, standards, and new techniques,” in Proc. EOS/ESD Sympo., 2000. [40] H. Wolf, H. Gieser, and W. Wilkering, “Analyzing the switching behavior of ESD-protection transistors by very fast transmission line pulsing,” in EOS/ESD Symp. Proc., 1999, pp.28-37. [41] C. Y. Chu and E. R. Worley, “Ultra low impedance transmission line tester,” in EOS/ESD Symp. Proc., 1998, pp.311-319.
|