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研究生:林琮富
研究生(外文):Tsung-Fu Lin
論文名稱:高速低成本的AES密碼運算晶片設計
論文名稱(外文):A High-Throughput Low-Cost
指導教授:吳誠文
指導教授(外文):Cheng-Wen Wu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
中文關鍵詞:密碼晶片對稱式密碼系統先進加密標準
外文關鍵詞:AEScryptosymmetric crypto-systemcipher
相關次數:
  • 被引用被引用:0
  • 點閱點閱:180
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  • 收藏至我的研究室書目清單書目收藏:0
先進加密標準 (Advanced Encryption Standard) 演算法是一種新型的對稱式加密系統,它是美國的國家標準及工業技術學會 (National Institute of Standards and Technology) 為了取代已經使用了超過三十年的資料加密標準(Data Encryption Standard) 所推動的一個新的密碼標準。近兩年來,有許多實現AES演算法的硬體已經被發表,但在這些電路的設計中,通常使用唯讀記憶體或隨機存取記憶體 (ROM 或 RAM) 來實現AES 演算法中一關鍵的構成要件 S-box,這種方式的好處是在硬體的實現上相當的方便,可以將所需要的結果直接使用查表的方式求得,但缺點是這種方式將會耗費較多的晶片面積。
在這篇論文中,介紹我們所採用的一種較經濟有效率的硬體實現方式。為了可以完整的實現AES 演算法,我們將密鑰擴展 (Key Expansion) 的程序也使用硬體電路實現。相較於廣泛使用的記憶體查表 (Table-Lookup) 的方法,我們所使用的方法在S-box的面積上可以達到64%的縮減;同時,管線化的架構使得我們的設計可以達到很高速的資料處理量。使用標準的 0.35微米互補式金氧半導體製程 (TSMC 0.35mm CMOS),我們的設計可以達到200 MHz的時脈速度, 當密鑰長度為128-bit 時每秒的資料處理量為2.381 Gbps,當密鑰長度為192-bit時每秒的資料處理量為2.008 Gpbs,當密鑰長度為256- bit時每秒的資料處理量為1.736 Gpbs;當使用標準的 0.25微米互補式金氧半導體製程 (TSMC 0.25mm CMOS)時,每秒的資處理量約增加為前述製程的1.25倍。最後,電路的可測試性也是我們一個設計的重點。

The AES (Advanced Encryption Standard) algorithm is a new standard of symmetric-
crypto system. It was announced by National Institute of Standards and Technology (NIST)
of the United States to replace the DES (Data Encryption Standard) algorithm and many
hardware implementations have been proposed. Most of these hardware design implemented
the key component, S-box, by the costly memory base method.
We propose an eÆcient hardware implementation of the AES algorithm, with key ex-
pansion capability. Compared with the widely used table-lookup technique, the proposed
basis transformation technique reduces the hardware overhead of the S-box by 64%. Our
pipelined design has a very high throughput rate. Using a typical 0:35m CMOS technology,
a 200MHz clock is easily achieved, and the throughput rate is 2.381 Gbps for 128-bit keys,
2.008 Gbps for 192-bit keys, and 1.736 Gbps for 256-bit keys. Testability of the design also
is considered. The hardware cost of the AES design is about 58.5K gates.

摘要………………………………………………………………………1
誌謝………………………………………………………………………2
目錄………………………………………………………………………3
第一章 序論……………………………………………………………4
第二章 AES 演算法介紹………………………………………………5
第三章 經濟有效率的S-box 實現方式………………………………6
第四章 AES 晶片架構…………………………………………………7
第五章 實驗結果………………………………………………………8
第六章 結論與未來展望………………………………………………9
英文附錄…………………………………………………………………10

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(AES). Springfield, VA 22161: National Technical Information Service, Nov. 2001.
[2] National Institute of Standards and Technology (NIST), Data Encryption Standard
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[4] IEEE, IEEE Standard Specifications for Public Key Cryptography. IEEE Standards
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didates using reconfigurable hardware," in Proc. 3rd AES Candidate Conference, 2000.
[8] M.-H. Li, \A Gbps AES cipher," Master Thesis, Dept. Computer Science, National
Tsing Hua University, Hsinchu, Taiwan, June 2001.
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of round 2 Advanced Encryption Standard algorithm," in Proc. 3rd AES Candidate
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[10] T. Ichikawa, T. Kasuya, and M. Matsui, \Hardware evaluation of the AES finalists," in
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[11] H. Kuo and I. Verbauwhede, \Architectural optimization for a 1.82 Gbits/sec VLSI
implementation of the AES Rijndael algorithm," in Cryptographic Hardware and Em-
bedded Systems (CHES) 2001 (C.K. Koc, D. Naccache, and C. Paar, eds.), no. 2162 in
LNCS, Springer-Verlag, 2001.
[12] V. Rijmen, \EAcient implementation of the Rijndael S-box."
http://www.esat.kuleuven.ac.be/~rijmen/rijndael/sbox.pdf.
[13] W. W. Peterson and E. J. Weldon, Jr., Error-Correcting Codes. Cambridge, MA: MIT
Press, 2 ed., 1972.
[14] R. Lidl and H. Niederreiter, Introduction to finite fields and their applications. Cam-
bridge, MA: Cambridge University Press, revised ed., 1994.
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tomatic generation of memory built-in self-test cores for system-on-chip," in Proc. Tenth
IEEE Asian Test Symp. (ATS), (Kyoto), pp. 91{96, Nov. 2001.

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