臺灣博碩士論文加值系統

系統晶片設計是現在的主流。因為有成本較低及開發時間短的優勢，越來越多的產品以系統晶片的方式來完成，不過它在測試上仍然有很大的問題。大部份的核心 (Core) 都鑲嵌在系統晶片的電路裡，很難從晶片的接腳去控制，因此我們需要有好的測試存取機制 (Test Access Mechanism) 來提供測試的路徑。隨著技術的進步，會有越來越多的核心被整合在一顆晶片中，如此導致測試成本，亦即測試時間及測試電路面積的增加。測試排程 (Test Scheduling) 的目的就是要在給定的限制及條件下，安排最好的核心測試順序及測試資源分配。為了解決系統晶片上的種種問題，測試排程和測試架構不再是獨立的問題，一個能整合這兩種方法的技術才是解決之道。
在這篇論文裡，我們提出了在單層TACS (Test Access Control System) 測試存取控制架構下做測試排程的演算法。單層TACS的測試架構只需要一個測試控制器來控制測試資源及核心測試，雖然會使得測試時間稍微增加，但測試電路的面積非常的小。我們提出了三個排程的演算法，同時用這三種演算法對系統晶片的核心測試做排程，以其中測試時間最短的為排程結果，如此可同時最佳化測試時間及測試架構。從實驗結果中顯示，我們所提出的方法只需要很小的面積就可以得到與其他方法很近似的測試時間，而且在控制核心測試方面也簡單許多，測試成本也隨之下降。

第一章　序論
第二章 測試架構
第三章 測試排程問題
第四章 單層TACS測試排程
第五章 實驗結果
第六章 結論與未來發展

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