臺灣博碩士論文加值系統

在嵌入式系統的設計中，減少功率消耗是相當重要的課題。在資料存取頻繁的應用上，例如語音或影像處理，記憶體系統所消耗的功率在整個系統的功率預算中佔有很大的比例。由於嵌入式系統使用的核心處理器在應用上具有很大的彈性，系統的效能並未針對特定的系統應用做最佳化；若要達到減少功率消耗的目的，在設計流程的每一步驟都必須加以考量。然而一個設計工程師往往無法熟知在每個設計階段所使用的方法，因此建立一個電腦輔助設計的環境有其存在的必要。
我們建構一個探討低功率嵌入式記憶體架構的電腦輔助設計環境，其中包含了高階記憶體模型的建立，用以在設計初期評估記憶體的特性；並且允許在功率消耗和所需代價之間作取捨。另一方面，對該系統的應用做記憶體使用狀況的分析，藉以獲得針對該系統應用的最佳記憶體架構。在這個環境之中，我們提出兩個因應不同的需求的演算法，自動化的探討可行的架構並找出最佳解。費伯納西演算法 (Fibonacci algorithm) 可產生與耗竭式演算法 (exhaustive algorithm) 相同的結果，並且其計算時間減少n倍，n為記憶體位址的數目。第二個演算法為離散演算法 (Discrete algorithm)，其產生的記憶體架構是由大小為2的指數次方的記憶體區塊所組成。由實驗結果顯示，透過我們所提出的方法，可以減少記憶體系統52%的能量消耗。

第一章　序論
第二章 低功率嵌入式記憶體設計
第三章 記憶體模型的建立
第四章 考量功率消耗之記憶體分割
第五章 實驗結果
第六章 結論與未來展望

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