臺灣博碩士論文加值系統

以小波轉換為基礎的影像壓縮技巧正廣泛地被較新穎的影像壓縮標準所採用,例如JPEG 2000 和 MPEG 4. 儘管小波轉換擁有較高的壓縮效率和壓縮彈性等優點,比較舊的影像壓縮技巧,離散餘弦轉換轉換,仍然被比較舊的影像壓縮標準,例如 MPEG1, MPEG2和H.263 所採用.因為如此,目前的影像壓縮技巧是離散小波轉換和離散餘弦轉換所用存的狀態,我們試著設計出一個離散餘弦轉換至離散小波轉換的轉碼器,如果我們擁有這種轉碼器,比較舊的影像壓縮技巧(離散餘弦轉換)和比較新的影像壓縮技巧(離散小波轉換)之間的不相容性將被解決.
如同被廣為所知的,離散小波轉換和離散餘弦轉換由各自的數學式子所組成,許多快速小波轉換和快速離散餘弦轉換正因為分解她們各自的數學式子而被發明出來,除了數學式子的分解之外,離散小波轉換和離散餘弦轉換所各自擁有的對稱性和本身濾波器係數的特性都能夠用來在硬體上加快他的運算速度和節省他的晶片面積.在我們目前的研究當中,我們用矩陣運算的方法去試著研究看看是不是存在著一些方法可以節省我們的轉碼器的運算時間和晶片面積,矩陣運算的研究方法和數學式子上的分解相當類似.因此,我們根據了矩陣運算的方法發展出了幾種離散餘弦轉換對離散小波轉換轉碼器的硬體設計.在這一篇論文當中,我們對我們的矩陣運算研究方法做了一個總結.有一些轉碼器擁有較小的晶片面積,運算時間卻較長.而有些運算時間會比較短,卻必須要犧牲一些晶片面積.
根據TSMC 所提供的.35 cell library, 我們所設計的轉碼器都能夠到達50MHZ的clock頻率,針對我們所設計出來的轉碼器的各項比較將會在這篇論文中說明.

The wavelet-transform based image compression technique has been widely used in the newest image compression standards, such as JPEG200 and MPEG4. In spite of high compression rate and flexibility in the ultilization of wavelet-transform, older image compression technique, DCT-transform is still used in the older image compression standards, such as MPEG1, MPEG2 and H.263. Because of the coexistence of DCT-transform and DWT-transform, we try to design a DCT to DWT transcoder. If we have this kind of transcoder, the incompatibility between older image compression standards and newer one will be resolved.
It’s well known that DCT-transform and DWT-transform are composed of their own mathematical equations. Many Fast DCT-transform and Fast DWT-transform algorithms have been developed by factorizing these equations. Beside factorization, some properties, like symmetry and particular coefficients can be used to speed up the hardware computation speed and reduce chip area. In our current research, we use matrix operation to investigate if there exists some ways to meet the requirements. This kind of investigation is similar to mathematical equation factorization. Accordingly, we have developed different kinds of hardware architectures of the DCT to DWT trascoder. In this thesis, we summarized our matrix operation investigation. Some architectures have less area but lower computation speed and others have higher computation speed but must sacrifice its own area.
By the TSMC .35um cell-library, each of the proposed transcoder in this research achieves 50-MHz working speed. Comparisons between each of them are shown later.

Chapter 1 Introduction
1.1 DCT-transform and DWT-transform
1.2 Motivation
1.3 Thesis organization
Chapter 2 Mathematical Theory on Transcoding
2.1 Overview of some transcoding methods
2.2 Mathematical theory on DCT-to-DWT transcoding
Chapter 3 Implementation of Transcoder Architecture
3.1.1 Investigation result of new transcoding theory
3.1.2 Lifting scheme
3.2 Hardware implementation of new transcoder architecture
3.3 A faster architecture design by new transcoding
algorithm
3.4.1 Systolic VLSI Architectures
3.4.2 Further consideration of DCT-to-DWT Systolic
Architectures
Chapter 4 Comparisons on Proposed Architectures
4.1 Lifting-based DCT-to-DWT transcoder architecture
4.2 Systolic-based DCT-to-DWT transcoder architecture
4.3 Comparisons between DCT-to-DWT transcoding designs
Chapter 5 Conclusion and Future works
Reference

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