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研究生:唐漢熙
研究生(外文):Hann-Shi Tong
論文名稱:爪哇處理器在內嵌入式Web伺服器上的電量分析
論文名稱(外文):Power Analysis of Java Processor for Embedded Web Servers
指導教授:許雅三金仲達金仲達引用關係
指導教授(外文):Yarsun HsuChung-Ta King
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:45
中文關鍵詞:內嵌入Web伺服器爪哇處理器電量分析
外文關鍵詞:embedded Web serverjava processorpower analysis
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隨著全球資訊網的發展,越來越多的家電可以透過網路連接上網際網路。假如這些家電能夠裝置內嵌入Web伺服器,使用者就可以透過Web瀏覽器在全世界各地來控制這些家電。因此內嵌入式Web伺服器的設計成為一個很重要的研究課題。其中一個研究方向就是建立內嵌入式Web伺服器的程式語言。爪哇語言由於其較安全、具有跨平台特性、且其程式碼較小(每一指令平均約1.8byte)、以及軟體的可重複使用性使得爪哇語言適合於建立內嵌入式Web伺服器。而目前執行爪哇語言的環境,爪哇處理器是最適合於內嵌入系統的。此外,在現今處理器的設計上,電量消耗、散熱問題也變得越來越重要,所以本篇論文就爪哇處理器上的內嵌入Web伺服器來探討電量以及效能平衡問題。我們採用了昇陽公司所發展的picoJava-II作為研究用的處理器,而且我們也就此處理器中的指令摺疊單元來探討電量和效能的平衡問題。
此外,我們採用惠普公司的ChaiServer作為我們的內嵌入Web伺服器而且我們也在ChaiServer執行時,動態擷取其指令執行的位元碼。然後利用trace-driven的模擬器來模擬picoJava-II在靜態式(pattern-based)和動態式(rule-based)的2-、3-及4-摺疊下的效能。然後我們把picoJava-II的RTL程式碼合成電路後用Synopsys所開發出來的電腦輔助設計程式來量測其電量消耗。模擬結果顯示靜態式的2-、3-及4-指令摺疊可分別省去30%、52%、53%的推疊運算。動態式的2-、3-及4-指令摺疊則可分別省去49%、83%、93%的推疊運算。此外,電量分析結果也顯示出動態式的2-指令摺疊有較低的電量效能比。

With the ubiquity of the World Wide Web (WWW), more and more appliances have networking capabilities and are hooked on the Internet. If they are embedded with a Web server, users can control these appliances through a Web browser anywhere in the world. Design of embedded Web servers thus becomes a very important research topic. One research issue is the choice of the programming language for building an embedded Web server. Java is a simple, small, secure and object-oriented language that promotes clean interfaces and software reuse. These features make Java an ideal tool for building an embedded Web server. Among the methods of executing Java bytecodes, Java processor is very suitable for embedded systems. Since power dissipation and thermal issues become increasingly significant in modern processor design, this thesis studies the power/performance of Java processors when used in embedded Web servers. We select Sun Microsystems picoJava-II as our reference and study its power/performance ratios for different folding models.
We construct an embedded Web server by HP ChaiServer and trace its bytecodes. Next, the performance of the picoJava-II with pattern-based and rule-based 2-foldable, 3-foldable and 4-foldable folding models are simulated and evaluated with a bytecode-level simulator. The power consumption of the simulated picoJava-II is obtained by synthesizing the RTL code of picoJava-II. Simulation results show that, the pattern-based 2-, 3-, 4-foldable strategies of picoJava-II can eliminate 30%, 52% and 53% stack operations in the HP ChaiServer trace file respectively. However, ruled-based folding can respectively eliminate 49%, 83% and 93% stack operations. Moreover, power analysis shows that the rule-based 2-foldable strategy has the lowest power/performance ratio.

Abstract Acknowledgements Contents List of Figures
List of Tables
1.Introduction 1.1Embedded Web Server
1.2Java Computing
1.3Power Analysis
1.4Organization of the Thesis
2.Survey 2.1ChaiServer
2.2PicoJava-II Architecture
2.3Instruction Folding
3.Experiment Methodology
3.1Simulator Overview
3.2Power Analysis
4.Simulation Results
4.1Characteristics at the Bytecode Level
4.2Performance of the Different Folding Models
4.3Power Consumptions of the Different Folding Models
5.Conclusions and Future Works Bibliography

[1] McCombie, B., “Embedded Web Servers now and in the future, “ Real-Time Magazine, no.1 March 1998, pp. 82-83.
[2] Wilson, A., “The Challenge of embedded Internet,” Electronic Product Design, January 1998, pp. 31-2, 34.
[3] Ian Agranat, “Embedded Web Servers in Network Devices,” Communication Systems Design, March 1998, pp. 30-36
[4] T. Lindholm and F. Yellin, The Java Virtual Machine Specification. Addison Wesley, 1997.
[5] M. Gowan, L. Biro, and D. Jackson. Power considerations in the design of the Alpha 21264 microprocessor. In 35th Design Automation Conference, 1998.
[6] V. Tiwari et al. Reducing power in high-performance microprocessors. In 35th Design Automation Conference, 1998.
[7] David Brooks, Vivek Tiwari, and Margaret Martonosi. Wattch: A Framework for Architecture-Level Power Analysis and Optimization. In Proceedings of the 27th International Symposium on Computer Architecture, pages 83-94, Vancouver, Canada, June 2000.
[8] Sun MicroSystems, picoJava-II Microarchitecture Guide, March 1999
[9] Sun MicroSystems, picoJava-II Programmer’s Reference Manual, March 1999
[10] Hewlett Packard Company, ChaiServer Guide Release 3.0 FCS, July 2000.
[11] G. Cai. And C. H. Lim. Architectural level power/performance optimization and dynamic power estimation. Cool Chips Tutorial collocated with MICRO32, November 1999.
[12] D.C. Burger and T.M. Austin. The SimpleScalar Tool Set,Versin 2.0. Computer Architecture News, pages 13-25, June 1997
[13] Sun Microelectronics, picoJava-I Microprocessor Core Architecture. http://www.sun.com/microelectronics/picoJava/, Oct. 1996.
[14] Lung-Chung Chang, “Stack Instruction Folding of Java Processor: Modeling and Realization”, PhD thesis, National Chiao Tung University, Hsin-Chu, Taiwan, Republic of China, April 2002.
[15] Sun Microelectronics, picoJavaTM Microprocessor Core Overview http://www.sun.com/microelectronics/picoJava/overview.html.
[16] Han-Min Tseng, Lung-Chung Chang, Lee-Ren Ton, Min-Fu Kao, Shi-Sheng Shang and Chung-Ping Chung, “Performance Enhancement by Folding Strategies of a Java Processor”, International Conference on Computer Systems Technology for Industrial Applications — Internet and Multimedia, April 1997.
[17] Lee-Ren Ton, Lung-Chung Chang, Min-Fu Kao, Han-Min Tseng, Shi-Sheng Shang, Ryeu-Liang Ma, Dze-Chaung Wang and Chung-Ping Chung, “Instruction Folding in Java Processor”, International Conference on Parallel and Distributed Systems. December 1997.

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