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研究生:李書榮
研究生(外文):Shu Rong Lee
論文名稱:嵌入式記憶體存取時間自我測試單元
論文名稱(外文):An Access Time Measurement Unit of Embedded Memory
指導教授:張慶元張慶元引用關係
指導教授(外文):Tsin Yuan Chang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:45
中文關鍵詞:測量嵌入式記憶體存取時間
外文關鍵詞:MeasurementEmbedded MemoryAccess Time
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在計算機系統中,記憶體的存取速度往往決定了此計算機的效能,而且隨著晶片系統整合及SoC(System on Chip)的技術來臨,不只是效能,記憶體更主宰了整個系統的良率。因此記憶體的測試與量測就變的日益重要了。在記憶體的測試中包含了邏輯方面功能的正確與否,同時也包含了重要的時間參數量測,因為時間參數決定了記憶體的等級與分類,甚至系統的成功與否。傳統的外部量測如ATE(Automation Testing Equipment),已漸漸無法追隨系統速度設計的進步,不單是速度方面,精確度也變成了一個問題,因此我們需要一個低成本,高精確度的內建式量測系統。對於憶體功能測試的問題,已經發展了內建自我測試BIST (Built-in-Self-Test) 技術,但是內建自我測試無法做到AC參數的測量。本文在內嵌SRAM的時間參數量測方面,提出了一個 「內建式的存取時間量測單元」(Embedded Access Time Measurement Unit) 之電路設計。此內建於記憶體中的時間對數位轉換(Time to Digit Conversion) 的單元以雙斜率時間對數為轉換器(Dual-slope TDC)為基礎而修改,可測得記憶體存取中最長的存取時間。這個分離式的時間對數為轉換器可與嵌入式記憶體同速的測量。由實驗結果在量測存取速度為1GHz (access time為1ns)時 ,其測量範圍為5ns時,精確度可做到50ps(5%),其平均誤差小於一個LSB,而線性失真為1.12%。當精確度提升為2%時,誤差為1個LSB。另外基於March演算法架構,此內建測量單元面積在2P4M CMOS製成下為262x92µm2。此量測單元提供SRAM設計者一個內建BISM (built-in self measurement)的構想,可同速(at-speed)且精準的測量Embedded memory中的存取時間,抑或其他的重要時間參數。

In a computer system, the speed of an embedded memory is usually a key factor of system performance. As the deep sub-micron techniques evolving, embedded memories are dominating the yield, while the testing and measurement issues are more difficult due to the access limitations. To solve the testing problem, BIST (built-in-Self-Test) circuits are developed for testing the functionality of embedded memory, but not for the AC parameters. An access timing measurement unit of embedded memory is proposed in this thesis. It consists of a TDC (time-to-digital converter) with the BIST. Based on the dual-slope principle, the modified TDC can measure the maximum access time of embedded memory. The measurement range is designed from 1ns to 5ns. It can achieve the at-speed measurement with 50ps resolution, where the measurement error is smaller than one LSB, and the linearity error is 1.19%. In conjunction with the March-based BIST circuit, the chip area is 262x92 m2 under 0.35m 2P4M CMOS process. This measurement unit with the built-in-self measurement method can achieve both advantages of at-speed and accurate measurement for memory access time.

論文摘要 1
誌謝 2
目錄 3
第一章 緒論4
第二章 先前的工作5
第三章 測量問題6
第四章 提出的測量架構7
第五章 結論與未來展望8
英文附錄9

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[2] T. I Otsuji, “A Pico second-accuracy, 700MHz Range, Si-Bipolar Time Interval Counter with 30ps Resolution” IEEE Journal of Solid- State Circuits, vol. 28, no. 9, pp. 941-947, 1993.
[3] E. Raisanen—Ruosalainen, T. Rahkonen, and J. Kostamovaara, “A BiCMOS Time to Digital Converter with 30ps Resolutions”, Proceeding of ISCAS, vol.1, pp.278-281, 1999.
[4] P. Chen, and S.I. Liu, “A Cyclic CMOS Time to Digital Converter with Deep Sub-nanosecond Resolution,” Proceedings of Custom-Integrated Circuit Conference, pp.605-608, 1999.
[5] E. Raisanen — Ruosalainen, T. Rahkonen and J. Kostamovaara, “A Low Power CMOS Time-to-Digital Converter”, IEEE Journal of Solid State Circuit, vol. 30, no.9, pp.984-990, 1995.
[6] E. Raisanen — Ruosalainen, T. Rahkonen and J. Kostamovaara, “Time interval Measurements Using Time-to Voltage Conversion with Build-in Dual-Slope A/D Conversion”, Proceeding of ISCAS, vol.5, pp.2573-2576, 1991.
[7] M. J. Hsiao, J. R. Huang, S.S. Yang and T. Y.Chang, “A Low-Cost CMOS Time Interval Measurement Core”, Proceeding of ISCAS, vol.4, pp.190-193 2001.
[8] Nai-Yin Sung and Tsung-Yi Wu, “A Method of Embedded Memory Access Time Measurement,” Proceeding of International Symposium Quality Electronic Design, pp.462-465, 2001
[9] R. Dekker, F Beenker, L. Thijssen. “A realistic fault model and test algorithm for static random memory” IEEE Transactions on CAD, Vol. 9(6), pp. 567-572, 1990.
[10] AJ. Van de Goor, Testing Semiconductor Memories : Theory and Practice, Gouda. The Netherlands :ConTex Publishing, 1998.
[11] K. Koli, K Halonen, ”Low voltage MOS-Transistor-only precision current peak detector with signal independent discharge time constant”, Proceedings of ISCAS, vol.3. pp. 1992—1995, 1997.
[12] Paul R. Gray and Robert G. Meyer, “Analysis and Design of Analog Integrated Circuits”, John Wiley & Sons, Inc., 1997.
[13] Robert A. Johnson and George Szentirmai, “Analog MOS Integrated Circuits for Signal Processing”, John Wiley & Sons, Inc. 1986.

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