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研究生:陳建成
研究生(外文):Jian-Cheng Chen
論文名稱:管線式處理器自動化測試程式產生器
論文名稱(外文):Automatic Test Program Generation for Pipelined Processor Cores
指導教授:張慶元張慶元引用關係
指導教授(外文):Tsin-Yuan Chang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
中文關鍵詞:測試程式管線式處理器
外文關鍵詞:Test ProgramPipelined Processor
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伴隨著積體電路製造技術的大幅提昇,系統單晶片已成為積體電路設計的趨勢。整合各種不同型態,特性的電路於單一晶片上,可以達到高效能,低耗能的需求。面對這種趨勢,在積體電路測試工程方面的發展亦跟著有所改變,不僅在測試方式上,甚至將測試需求直接以電路設計滿足後段測試流程所需要的要求,即所謂之測試需求電路化(Design for Testability)。在系統單晶片中,往往具有一微處理器會為控制器,本論文所針對的問題即是:針對系統單晶片中的微處理器的管線結構(Pipeline Architecture),設計一可合成測試程式的流程,並驗證其可行性。測試程式由原來微處理器的指令集所組成,並且利用指令集形式合成測試程式可以達到即時測試(at-speed testing)流程的需求。
測試程式的流程主要分為三部分。第一部份,利用微處理器管線結構的特性,將設計分成數個部分,Sequential電路部分完全由微處理器模擬器所模擬,僅有combinational電路依據所需要falut形式,使用不同的自動測試對生成器(ATPG)進行模擬。因本論文所使用的ATPG
需要兩兩成對的測試指令集,因此指令集兩兩成對進入指令集模擬器進行測試。其測試項目主要是針對部分指令之間存在依存或互斥關係,因此無法完全形成兩兩成對型態,而這型態的指令集可先行濾出,以免增加流程時間複雜度(Time Complexity),而造成後續流程的時間損耗。微處理器模擬器輸入分析出的指令對,將分離數部分的電路信號予以連結並整理出條件相依圖形(Constraint Correlation Graph)。第二部份,根據條件相依圖形所整理出的測試指令對,利用現有的 Combinational ATPG生成有效測試指令對。此一流程的另一優點亦即在此凸顯,事實上,若是另用其他的 Combinational ATPG 可以生成針對不同 fault 形式的有效測試指令對,只要該電路設計及流程可以滿足第一部份的需求。第三部份,連結所有有效測試指令對成為測試程式,主要利用原則有條件相依圖形所產生的指令連結條件,以及使用者的額外設定,例如程式檔頭或是檔尾。
最後,本論文以一個ARM 7 相容微處理器進行測試程式合成的流程驗證。而硬體結構描述配合指令分析所得到的條件相依圖形(Constraint Correlation Graph)有效地驗證指令對符合執行條件以成為測試模式指令對,減少自動測試對生成器(ATPG)所需的有效指令對(DeterministicPattern Pair)運算時間,因為有效指令對只佔整個指令對組合(Pattern Pair Set)的一部份。進一步,再將輸出有效指令對合成為微處理器測試程式。

The proposed instruction set test program aims the at-speed functional testing for pipelined processor core. If the processor design is based on Harvard structure, the proposed method can provide effective method to extract the constraints for functional level testing. Especially for the pipeline structure, the processor can be divided into several blocks, and each block can be individually analyzed. By observing the register bank and pipeline register, the proposed methodology provides an automatic and efficient flow to generate the test for the targeted fault with an instruction-level simulator and a gate-level ATPG. In this thesis, through instruction-level simulator, a flexible mechanism is provided to extract functional constraints of each pipeline stage to minimize unnecessary backtracking on internal signals imposed on gate-level ATPG. Given the generated constraint graph and additional user definitions, the test program can be synthesized by analyzing the correlations among general/pipeline/status registers, control signals, and constraints can be extracted. Applying the technique to the ARM 7 compatible processor core, such extracted constraints are applied to efficiently reduce the length of test patterns for identifying functional faults and to illustrate how to use generated constraint graph for each pipeline stage for integrating tests for the processor core.

Chapter 1 Introduction
1.1 Background ...................................... 1
1.2 Functional tests development ..................... 3
Chapter 2 Framework
2.1 Goal ............................................. 7
2.2 Proposed Flow .................................... 8
Chapter 3 Constraint Extraction
3.1 Representation of Instruction-set Architecture .. 14
3.2 Representation of Processor Architecture ........ 18
3.3 Instruction-Level Simulator ..................... 20
3.4 Bit-level Analysis .............................. 24
Chapter 4 Test Program Synthesis
4.1 Test Pattern Generation ......................... 26
4.2 Test Pattern Mapping and Classification ........ 27
4.3 Resource Assignment and Redundant Insertion ..... 28
Chapter 5 Experiment
5.1 Processor Core For Experiment ................... 32
5.2 Constraint Extraction ........................... 38
5.3 Program Synthesis ............................... 42
Chapter 6 Conclusion and Future Work
6.1 Conclusion ...................................... 44
6.2 Future Work ..................................... 44
Reference .............................................. 46

[1] W.-C. Lai, A. Krstic, and K. T. Cheng, “On testing the Path Delay Faults of a Microprocessor Using its Instruction Set,” Proceeding of IEEE VLSI Symp., pp 15-20, May 2000.
[2] J.R. Huang, M.K. Iyer, and K.T. Cheng, “A Self-Test Methodology for IP Cores in Bus-based Programmable System-on-a-chip”, Proceeding of IEEE VLSI Test Symp.”, May 2001.
[3] Steve Furber. ARM System Architecture, Addison-Wesley Longman, 1996.
[4] L. Chen and S. Dey. DEFUSE, “A Deterministic Functional Self-Test Methodology for Processors,” Proceeding of IEEE VLSI Test Symp.”, pp 255-262, May 2000.
[5] A.E. Salama, A.K. Ali, and E.A. Taikhan, “Functional Testing of Pipelined Processors”, IEE Proc-Comput. Digit. Tech., Vol 143, No 5, pp 318-324,September 1996.
[6] Junichi Hirase and Shinichi Yoshimura, “Faster Processing for Microprocessor Functional ATPG”, IEEE Proceedings of the Ninth Asian, pp 191-197, 2000.
[7] Raghuram S. Tupuri and Jacob A. Abraham, “A Novel Functional Test Generation Method for Processors using Commercial ATPG”, IEEE International Test Conference ,pp 743-752, November 1997.
[8] Michael L. Bushnell, Vishwani D. Agrawal, Essential of Electronic Testing For Digital, Memory And Mixed-Signal VLSI Circuits, Kluwer Academic Publishers, pp.466, 2000
[9] M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design, Piscataway, New Jersey: IEEE Press, 1994.

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