臺灣博碩士論文加值系統

相對於市場主流的CCD (Charge-Coupled Device)影像感測器而言，CMOS影像感測器因為有成本較低，整合容易及消耗功率較低的優點，近年來逐漸受到矚目。因為工作電壓較低所造成的感測範圍較小的問題，也有許多人探討和改善。感測器中除了光-電轉換電路外，還可以整合類比至數位轉換器進去，使得輸出資料即為數位資料。
本篇論文描述一個針對CMOS影像感測器，可改善整體轉換特性的非線性類比至數位轉換器設計。這個類比至數位轉換器利用非線性轉換特性來使輸出資料中包含較多低亮度的資料，使得8位元的輸出資料在需要高解析度的低亮度可以達到10位元的有效解析度。藉由平滑的轉換曲線，它可以微調入射光強度至輸出資料間的轉換特性，產生比較理想的轉換特性。
這個類比至數位轉換器在實現時整合在一個176x144像素的CMOS影像感測器中，以台積電(TSMC) 0.35um 1P4M製程製作。它的操作電壓3.3V，輸入範圍0-1.5V，轉換速度1Ms/s。為了面積與消耗功率上的考量，它採用持續近似架構。其中含有的主要建構元件為取樣電路、控制電路、轉換電路、數位至類比轉換器和自我測試電路，而其中的數位至類比轉換器以電流驅動架構實現。自我測試電路可以對類比至數位轉換功能的正常與否做自我測試。以Avant! Hspice做佈局後模擬所得結果，它消耗的功率為17.12mW，其中類比部分電路佔了61.7%，其轉換曲線的線性誤差最大值為0.42LSB而它所佔面積為240000 um2。

Advantage of CMOS image sensor such as high integration and low power makes this kind of image sensor have its position. But tradeoff between dynamic range and output swing is undesirable. In this thesis, a nonlinear A/D converter design for CMOS image sensor is described and designed with a 0.35 um 1P4M process. The nonlinear transfer function of the proposed A/D converter changes the resolution distribution of the output data, thereby improving the overall sensor’s resolution in low illumination and overcoming the effect of the sharp break point in the pixel cell’s photo-electrical characteristic.
The A/D converter uses successive-approximation register architecture with current-mode D/A converter. It has input range of 0V to 1.5V and 8-bit output data. The total power consumption is 17.12mW and the total area is about 240000 um2.

Contents
1 Introduction 1
1.1 Motivation…………………………………………………………… 2
1.2 Thesis Organization……………………………………………… 2
2 Background 3
2.1 CMOS Image Sensor……………………………………………… 3
2.1.1 Architecture…………………………………………………… 3
2.1.2 Active Pixel Sensor………………………………………… 3
2.2 A/D Converter categorization………………………………… 7
3 Previous Work 12
4 Design and Consideration 15
4.1 Architecture……………………………………………………… 15
4.2 Transfer Logic…………………………………………………… 16
4.3 Control Circuit and Registers………………………………… 17
4.4 Sample-and-hold Circuit………………………………………… 18
4.5 Comparator………………………………………………………… 19
4.6 D/A Converter……………………………………………………… 22
4.7 Built-in Self Test……………………………………………… 24
4.8 Noise Consideration……………………………………………… 25
4.8.1 Switch…………………………………………………………… 25
4.8.2 Noise from Cell Array and Digital Circuit…………… 26
4.9 Layout Consideration…………………………………………… 26
4.9.1 Floor-plan……………………………………………………… 26
4.9.2 Layout of D/A Converter…………………………………… 27
5 Experimental Result 28
5.1 Parameter…………………………………………………………… 28
5.2 Simulation Result………………………………………………… 29
5.3 Layout of components and A/D converter…………………… 33
6 Conclusion 35
Appendix 36

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