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研究生:林昌輝
研究生(外文):CHANG HUI LIN
論文名稱:第三代行動通訊渦輪解碼器之分析與硬體研製
論文名稱(外文):An Investigation and Hardware Architectural Implementation of Turbo Decoder
指導教授:鐘太郎
指導教授(外文):Tai-Lang Jong
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:德文
論文頁數:89
中文關鍵詞:渦輪碼最大事後機率軟式輸出緋特比演算法
外文關鍵詞:turbo codeMAPSOVA
相關次數:
  • 被引用被引用:2
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渦輪碼 (turbo code) 是由Berrou等人於1993年所提出來的一種錯誤更正碼技術。此種錯誤更正碼技術是當代編碼理論的一大突破,因為它在相當低的訊號雜訊比中仍可以使數位通訊系統具有低的位元錯誤率,所以被選擇於第三代行動通訊系統的通道編碼解碼方法之一。第三代行動通訊系統的標準規範被定義於IMT-2000 (International Mobile Telecommunications-2000),IMT-2000 是由 ITU (International Telecommunication Union) 所定義。其位元傳輸率為到大部分地區:384 kbit/s,室內或靜止狀態:2 Mbit/s或更高。歐洲的WCDMA系統 與 北美的CDMA-2000 系統為第三代行動通訊系統的主要兩大方案,兩者的渦輪碼編碼器皆由兩個相同的8-state迴旋編碼器(convolutional encoder) 及一個交錯存取器所組成。而渦輪解碼器 (turbo decode) 主要是由兩個具有軟式輸入 (soft-input) 及軟式輸出 (soft-output) 的迴旋解碼器和一組交錯存取器所組成並以反覆解碼的架構來解碼。
用於軟式輸入軟式輸出解碼器的演算法,主要可分為軟式輸出緋特比演算法 (SOVA) 與最大事後機率 (MAP) 演算法兩大類。每種演算法具有不同的錯誤更正效果及運算複雜度,越好的錯誤更正效果通常伴隨著越複雜的運算複雜度。在本篇論文中,我們首先將探討這些演算法的運算原理以及降低運算複雜度的技巧。接下來,我們分析各種演算法的運算的運算複雜度與模擬在CDMA-2000 系統下,各種硬體設計上的考量與不同演算法間的錯誤更正效果。從這些分析與模擬結果,我們在錯誤更正效果及運算複雜度間做一取捨,選擇Max-Log-MAP演算法作為軟式輸入軟式輸出解碼器的演算法。依循這些模擬參數,我們設計一個全新架構的渦輪解碼器,此解碼器是依照 CDMA-2000 系統之規範,傳輸率可達到2 Mbit/s,並且可成功合成於FPGA上。
Contents II
List of Figures V
List of Tables VII
List of Notations VIII
List of Acronyms XI
Chapter 1 Introduction 1
1.1 Fundamental Limits 1
1.2 Related Work 3
1.3 Major Contributions of the Thesis 4
1.4 Thesis Outline 4
Chapter 2 Turbo Codes System 5
2.1 Element of a Digital Communication System 5
2.2 Turbo Encoder 6
2.2.1 Turbo Encoding of CDMA2000 6
2.2.2 Block Size and Data Rate 6
2.2.3 Constituent Encoder 7
2.2.4 Puncture Table and Repetition 9
2.2.5 Turbo Interleavers 10
2.3 Turbo Decoder 11
2.3.1 Turbo Decoder System 11
2.3.2 MAP Algorithm 12
2.3.2.1 Branch Metric 13
2.3.2.2 Forward Recursion 14
2.3.2.3 Backward Recursion 16
2.3.2.4 Log Likelihood Ratio 17
2.3.2.5 Extrinsic Information 18
2.3.3 Log-MAP algorithm 20
2.3.3.1 Forward Recursive 21
2.3.3.2 Backward Recursive 22
2.3.3.3 Log Likelihood Ratio 23
2.3.4 Max-Log-MAP algorithm 24
2.3.4.1 Forward Recursion 24
2.3.4.2 Backward Recursive 25
2.3.4.3 Log Likelihood Ratio 25
2.3.5 Sliding Windows MAP algorithm 26
2.3.6 Another Ways to Reduce Complexity 27
2.3.7 Original SOVA Algorithm 30
2.3.7.1 Viterbi Algorithm 30
2.3.7.2 Extrinsic Information of Original SOVA 32
2.3.8 Modified SOVA Algorithm 35
2.3.9 Another Ways to Simplify SOVA algorithm 36
2.3.11 Comparison for Each Decoding Algorithm 39
2.3.11.2 Memory Usage for Decoding Algorithms 42
2.4 Conclusion 42
Chapter 3 Simulation and Analysis of Turbo Decoder Algorithms 44
3.1 Simulation of MAP Algorithm 44
3.1.1 Simulation of MAP for Different Block Sizes 44
3.1.2 The Effects of Overlap-Length 46
3.1.3 Simulation of the Effect of Extrinsic Information 47
3.1.4 Simulation of the Effects of Quantization 49
3.1.5 Simulation of the Effect of Sliding window 50
3.2 Simulation of Log-MAP Algorithm 51
3.2.1 Simulation of the Effect of Overlap-Length 51
3.2.2 Simulation of the Effect of Quantization 53
3.3 Simulation of Max-Log-MAP Algorithm 54
3.3.1 Simulation of the Effect of Overlap-Length 54
3.3.2 Simulate the Effect of Quantization 56
3.4 Simulation of the Original SOVA 57
3.5 Simulation of Modified SOVA 59
3.6 Simulation of A Posterior Weighting Algorithm 60
3.7 All Algorithms 61
3.7 Conclusion 63
Chapter 4 VLSI Implementation of Turbo Decoder 64
4.1 Architecture of Top-Level Decoder 64
4.1.1 Receiving Data and Decoding Procedure 65
4.1.2 Decoding Procedure of a Frame 65
4.1.3 Decoding Procedure of a Constituent Decoder 65
4.1.4 Pipeline Execution of the Decoding Procedure for a SW 66
4.2 FIFO Module 68
4.3 I/O-Controller Module 68
4.4 Turbo-decoder module 69
4.4.1 Architecture of ACS Component 69
4.4.1.1 Radix-2 ACS Component 69
4.4.1.2 Radix-4 ACS Component 70
4.4.2 Architecture of ACS Array 71
4.4.3 Normalization of Alpha and Beta 73
4.4.4 Architecture of Lambda Array 73
4.4.5 Amount of words of alpha memory 75
4.5 Implement of Turbo Decoder by FPGA 76
4.5.1 Design Flow 76
4.5.1.1 ASM Chart of Turbo Decoder 77
4.5.1.2 Implicit Style Behavioral Module 78
4.5.1.3 Structural Module 79
4.5.1.4 Simulation 79
4.5.1.5 Timing Analysis and Design Modification 81
4.6 Conclusion 82
Chapter 5 Conclusion 84
5.1 Conclusion 84
5.2 Future Work 84
Bibliography 85
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