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研究生:王泓斌
研究生(外文):Horng-Bin Wang
論文名稱:用於診斷邏輯晶片內延遲瑕疵之類針灸式方法研究
論文名稱(外文):Gate-Delay Fault Diagnosis Using The Inject-And-Evaluate Paradigm
指導教授:黃錫瑜黃錫瑜引用關係
指導教授(外文):Shi-Yu Huang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:32
中文關鍵詞:延遲瑕疵
外文關鍵詞:delay fault diagnosis
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摘要
早期對於數位IC電路設計,電路函數(function)的正確與否是從事研發設計人員最為關心的因素。伴隨著半導體製程技術的改進,我們對IC工作速度的要求也越來越嚴格,也因此時脈頻率的快慢成為影響產品品質的一個重要指標。為了保證產品能夠符合時脈效能的規則,延遲瑕疵診斷的需求以成為刻不容緩的課題。
 延遲瑕疵的診斷,不論在工業界或學術界都已成為一項新的研究話題。儘管一些延遲瑕疵的模型(model)及診斷的方法已被普遍的提出,不過極大部分的診斷方式仍偏重在於向後追溯(backtrace)演算法的應用,此種向後追溯演算法尋找延遲發生點,主要藉由個別獨立追溯瑕疵晶片輸出端的錯誤症狀(syndrome)往前推向輸入端,之間經過的點皆視為可疑點。不幸的是此種演算法在面針於錯誤遮蔽效應(fault masking),短時脈衝波干擾的反應(response of glitch)及延遲瑕疵的大小皆無法提供一個好的解決方法。 
 這篇論文引介一種針對邏輯晶片內延遲瑕疵之類針灸診斷法,此種方法主要是一種針對及閘延遲瑕疵診斷的演算法。此種演算法主要依據六個代數的模擬(six-value simulation),並藉由一連串的注射和評估(inject-and-evaluate)而將最可疑的點累積到最高的積分。因為同時考慮了瑕疵晶片輸出端的錯誤症狀,此種向前推演(forward)的技巧,提供較高的準確性。我們的演算法也將短時脈衝波干擾的效應考慮在內,因此當脈衝干擾輸出端時或延遲瑕疵尺寸略小時,此法依然適用。最後實驗數據也證明了,經由此方法診斷出的延遲可疑數目,平均只有4.8個且只需花費不到十秒的時間。

Abstract
For many high-performance IC designs, the verification of timing is essential yet challenging. After manufacturing, certain defects may cause some chips to fail in timing. In order to improve the manufacturing yield and shorten the time-to-production, delay fault testing and diagnosis is often necessary. Delay diagnosis has been a topic of extensive research both in industry and in academia. Several delay fault models and testing methodologies have been proposed. However, these methods are not adequate in terms of the accuracy.
This thesis introduces a new algorithm for gate-delay fault diagnosis. It is based on the inject-and-evaluate paradigm [1], in which the fault site(s) are predicted through a series of injections and evaluations. Unlike the backtrace algorithm that predicts the fault site by tracing the syndromes at a faulty output back into the circuit, this approach mainly relies on the six-valued simulation. In such a forward approach, the accuracy is much higher because all the composite syndromes at all faulty outputs are considered simultaneously. We also analyze the effects of glitches and take them into account in our algorithm. As a result, the proposed approach is still applicable even when there are glitching outputs or when the delay size is relatively small. Experimental results show that the number of fault candidates produced by this approach is only 4.8 within 10 seconds of CPU time.

Contents
1 Introduction 2
1.1 Problem Addressed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Organization of This Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2 Preliminaries 5
2.1 Delay Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 Gate Delay Fault Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 Path Delay Fault Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Previous Work on Delay Fault Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 Cause-Effect Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.2 Effect-Cause Methodology.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 The Inject-and-Evaluate Paradigm 10
3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10
3.1.1 Fault Masking Effect .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1.2 Effect of Multiple-Path Sensitization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2 Basic Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Overview of the Diagnosis Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1 Phase 1: Fault Free Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.2 Phase 2: Symbolic Delay Propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.3.3 Phase 3: Matching Degree Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.3.4 Phase 4: Ranking Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4 Experimental Results 26
4.1 The Diagnosis Performance with One Gate-Delay Fault . . . . . . . . . . . . . . . . . . . . . 26
4.2 The Relation of First-Hit Index and Vector-Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.3 The Diagnosis Performance with Double Gate-Delay Faults . . . . . . . . . . . . . . . . 28
5 Conclusions 30
6 Bibliography 31

Bibliography
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[2] K. D. Wagner, “The error latency of delay faults in combinational and sequential circuits,” Proc. International Test Conference, pp. 334-341, (Nov. 1985).
[3] B. R. Waicukauski, J. A. Lindbloom, and V. Iyenger, “Transition fault simulation,” IEEE Design and Test, vol. 4, pp. 235-248, (1980).
[4] W.-N. Li, S. M. Reddy, and S. K. Sahni, “On Path Selection in Combinational Logic Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(1):56-63, (January 1989).
[5] C. J. Lin and S. M. Reddy, “On delay fault testing in logic circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 694-703, (Sept. 1987).
[6] Y.-C. Hsu and S. K. Gupta, “A New Path-Oriented Effect-Cause Methodology to Diagnose Delay Failures,” Proc. of International Test Conference, pp.758-767, (1998).
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[8] T. Haniotakis, E. Kalligeros, D. Nikolos, G. Sidiropulos, Y. Tsiatouhas, and H. T. Vergos, “A Class of Easily Path Delay Fault Teatable Circuits,” Southwest Symposium on Mixed-Signal Design, pp.165- 170, (2000).
[9] H.-C. Kao, M.-F. Tsai, S.-Y. Huang, C.-W. Wu, W.-F. Chang, and S.-K. Lu, “Efficient Double Fault Diagnosis For CMOS Logic Circuits,” Proc. of 12th VLSI/CAD Symposium, Taiwan, (Aug. 2001).
[10] G. L. Smith, “Model for delay faults based upon paths,” Proceedings of IEEE International Test Conference, pp. 342-349, (Nov. 1985).
[11] I. Pomeranz and S. M. Reddy, “On Correction of Multiple Design Errors,” IEE Trans. On Computer-Aided Design, vol. 14, pp. 255-264, (Feb. 1995).
[12] R. K. Brayton et al, “SIS: A System for Sequential Circuit Synthesis,” University of California, Berkeley, Tech. Report, (1992).
[13] S. Venkatraman and W. Fuchs, “A Deductive Techniques for Diagnosis of Bridging Faults,” Proceedings IEEE International Conference on Computer-Aided Design, pp. 562-569, (1997).
[14] C. J. Lin and S. M. Reddy, “On delay fault testing in logic circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 694-703, (Sept. 1987).
[15] J. H. Patel, K. Heragu, and V. D. Agrawal, “Segment Delay Faults: A New Fault Model,” Proceedings of 14th IEEE VLSI Test Symposium, pp. 32-39, (May 1996).

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