臺灣博碩士論文加值系統

快閃記憶體係一種可程式化及可抹除記憶資料之非揮發性記憶元件。在系統晶片(System-on-a-Chip)裡面，嵌入式快閃記憶體扮演著愈來愈重要的角色，尤其是應用在使用電池的電子產品上。隨著快閃記憶體的密度和容量愈來愈高、系統晶片所包含的核心(core)愈來愈複雜，造成測試的時間也跟隨著成長、測試成本因此大幅增加，導致嵌入式快閃記憶體的測試及診斷成為系統晶片在開發和生產階段的關鍵問題。
在這篇論文裡面，我們提出了一個對角線式的快閃記憶體測試方法，它能在維持很高的錯誤涵蓋率(fault coverage)的條件下，有效地減少整體的測試時間，無論是快閃記憶體特有的干擾錯誤(disturb fault)，或是傳統式記憶體常見的錯誤都可以被這種測試方法所涵蓋。除了測試方法以外，我們另外還提出了一個對角線式的診斷方法，它能夠用來區分快閃記憶體各種的干擾錯誤，以及大部份傳統式記憶體常見的錯誤。最後，我們提出一個內建式自我測試/診斷(BIST/BISD)電路的設計，它不但能夠有效地執行我們提出的測試及診斷演算法，同時也能執行使用者自行定義的演算法。這個電路的面積非常地小，它只需要使用2,551個邏輯閘來完成，它約佔一顆2Mb快閃記憶體總面積的2-3%左右。從實驗的結果顯示，我們提出的測試方法和另一種常用的March測試方法比較起來，測試時間大約可以減少42.69%左右，測試成本也可因此而大幅降低。

Embedded flash memory plays an increasingly important role for system-on-chip (SOC), especially for battery-powered devices.Testing and diagnosis of embedded flash memory is becoming one of the key development and production issues for many SOC products. Moreover, high density, high capacity, and the integration of heterogeneous cores in an SOC results in long
test time, which in turn lead to high test cost.
In this thesis, we propose a new diagonal test algorithm
for flash memory that effectively reduces the test time without
sacrificing the fault coverage. Both disturb faults and
conventional RAM faults are covered. A diagnostic algorithm
is also presented, which can distinguish among all the disturb
faults and most of the conventional RAM faults.
Finally, a built-in self-diagnosis (BISD) scheme is proposed.
The BISD circuit implements our algorithms and user-defined
ones, and its area overhead is low, e.g., it contains only
about 2,551 gates (2-3%) for a 2Mb flash memory. The test
time by our diagonal test is reduced by about 42.69% as
compared with the best March-like algorithm reported so far.

摘要………………………………………………1
誌謝………………………………………………2
目錄………………………………………………3
第一章 導論……………………………………4
第二章 背景資料與回顧………………………5
第三章 錯誤模式的定義………………………6
第四章 測試演算法……………………………7
第五章 診斷演算法……………………………8
第六章 內建式自我測試與診斷電路…………9
第七章 實驗結果……………………………10
第八章 結論與未來展望……………………11
英文附錄 ………………………………………12

[1] A. K. Sharma, Semiconductor Memories: Technology, Testing, and Reliability. Piscataway:
IEEE Press, 1997.
[2] P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memories. Boston: Kluwer Academic
Publishers, 1999.
[3] IEEE, IEEE 1005 Standard Definitions and Characterization of FloatingGate Semiconductor
Arrays. Piscataway: IEEE Standards Department, 1999.
[4] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. Gouda, The
Netherlands: ComTex Publishing, 1998.
[5] M. G. Mohammad, K. K. Saluja, and A. Yap, “Testing flash memories,” in Proc. 13th Int.
Conf. VLSI Design, pp. 406—411, Jan. 2000.
[6] M. Mohammad and K. K. Saluja, “Flash memory disturbances: modeling and test,” in Proc.
IEEE VLSI Test Symp. (VTS), (Marina Del Rey, California), pp. 218 —224, Apr. 2001.
[7] J.-C. Yeh, C.-F. Wu, K.-L. Cheng, Y.-F. Chou, C.-T. Huang, and C.-W. Wu, “Flash memory
built-in self-test using march-like algorithms,” in Proc. IEEE Int. Workshop on Electronic
Design, Test, and Applications (DELTA), (Christchurch), pp. 137—141, Jan. 2002.