臺灣博碩士論文加值系統

在這篇論文當中，我們提出一個對於處理器(Processor)有效率的測試方法，從處理器的規格(Specification)及設計階段中，萃取出每一個管線級(Pipeline Stage)可能的輸入限制(Input Constraint)，這些限制描述了處理器在執行指令的過程中可能的輸入情況。將這些輸入限制配合自動測試樣本產生器(Automatic Test Pattern Generator)產生出每一管線級的測試樣本(Test Pattern)。由於我們將輸入限制在處理器運作時可能的輸入範圍內，所以自動測試樣本產生器所需要考慮的錯誤(Fault)範圍縮小，所需的測試樣本產生時間也可以相對縮短。同時，因為這些測試樣本在產生之前已經加入了處理器功能性的限制，我們可以將其轉換成為處理器的指令(Instruction)。在測試時，從處理器的外部直接下達轉換得到的指令，便可以將電路中的錯誤活化(Activate)。為了驗證我們的方法，我們建構了一個以ARM (The Acorn RISC Machine) 指令級為基礎的處理器，做為我們的測試樣本。
因為測試所造成之處理器的影響方面，由於我們是針對處理器的特性來設定每一管線級的可能之輸入組合，並不是採取常見的掃瞄鏈(Scan Chain)的方式，所以可以將測試所造成的速度降低(Speed Degradation)及面積花費(Area Overhead)完全消除，對於速度要求嚴格的處理器來說，這個方法可以有效維持原有的速度表現。同時我們可以看到，這種方法可以讓原本自動測試樣本產生器無法產生測試樣本的錯誤，藉由此種方法，將不會造成影響的錯誤忽略，將錯誤涵蓋率(Fault Coverage)提高。在我們設計的處理器中，其錯誤涵蓋率可達到100%。

A functional test methodology for processor is introduced in this thesis. A processor core based on ARM instruction set is applied as the target processor. When we have functional constraints on individual stage and with proper design rules and partition of processor core, we can use a combinational ATPG tool to generate test patterns for each stage of the processor core. Then the processor can be tested by test instructions. This thesis focuses on single stuck-at functional faults of processor cores. Input constraints of each stage are applied to the ATPG to restrict the input space to functional one. As the constraints increase, more efficient test patterns can be obtained. This method also reduces the test pattern generation time. On the other hand, because this does not change the processor core structure, the proposed methodology has zero speed and area overhead, which is an important feature for timing and area critical designs.

摘要……………………………………………………………………i
誌謝……………………………………………………………………ii
目錄……………………………………………………………………iii
第一章 簡介………………………………………………………iv
第二章 先期的研究………………………………………………v
第三章 提出的功能性測試方法…………………………………vi
第四章 實驗結果…………………………………………………vii
第五章 結論與未來展望…………………………………………viii
英文附錄………………………………………………………………ix

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