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研究生:蘇恆毅
研究生(外文):Heng-I Su
論文名稱:適用於內嵌式處理器設計之指令集架構模擬器
論文名稱(外文):An Instruction Set Architecture Simulator for Embedded Processor Design
指導教授:吳誠文
指導教授(外文):Cheng-Wen Wu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:58
中文關鍵詞:指令集架構模擬器架構描述語言指令集模擬器
外文關鍵詞:Instruction Set Architecture SimulatorArchitecture Description LanguageInstruction Set Simulator
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嵌入式處理器在每個階段的設計評估,都是相當重要的課題,尤其是在架構層次 ( Architecture Level ) 上的評估更為重要。精確的評估在架構層次上,將是改善整體系統效能的重要關鍵。以架構層次上來看,整體的設計是不容易去決定的,設計者必須去花費相當多的時間在探索不同架構,針對相對應的應用程式,去決定最後的架構,如果沒有適當的模擬工具去輔助設計者來評估效能,那將會讓完整架構的決定,變成相當困難。指令集架構模擬器 ( Instruction Set Architecture Simulator ) 就是用來試圖去將上述的工作簡單化。
在本篇論文中,我們提出一個主要是針對嵌入式處理器設計的指令精確 ( Instruction-accurate ) 以及週期精確 ( Cycle-accurate ) 之指令集架構模擬器。模擬器可以幫助我們快速且容易去描述不同的嵌入式處理器,藉著我們所發展的一個簡單的架構描述方法 ( Architecture description )。根據模擬器產生的模擬結果,可以幫助我們很容易地去選擇一個具有高效能架構,而且額外增加的面積是在我們可接受的範圍之內。針對相關應用軟體發展,一個可除錯環境 (Debugging Environment ) 提供在我們的模擬環境中。另外為了因應某些處理器的特殊運算碼 ( Opcode )是模擬器中沒有提供的,我們提供一個可以更改模擬器程式原始碼,來增加新運算碼的修改環境。在我們的實驗中,我們針對不同架構去模擬和評估,根據所得的模擬結果,去修改架構來增進效能。在實驗的例子中,效能增進大約在百分之十九到百分之四十二左右。

The design evaluation of embedded processors at each level is an important issue, the architecture level especially. The accurate evaluation at the architecture level is the key to improving the system performance, but it is not easy to fix the complete design at the architecture level. The designers need to spend a lot of time in exploring different architectures based on the applications. Without an appropriate simulation tool for performance evaluation, exploring different processor architectures would be painful, if possible. An instruction set architecture simulator is a simulation tool which attempts to simplify this work.
In this thesis, we propose an instruction-accurate and cycle-accurate instruction set architecture simulator for embedded processor design. It helps us easily and quickly describing different embedded processors, using a simple architecture description method which we developed. According to the simulation results, it is easy for us choose the highest performance architecture with an acceptable area overhead. A debugging environment also is provided for debugging, which is important for application software development. It allows easy modification of the source code. If there are some special opcodes which our simulator does not support, one can revise the source code with the proposed environment. In our experiment, we simulated and evaluated the performance of some processor architectures. Based on the results, we were able to modify the architectures to improve their performance. The performance improvement varies from 19% to 42% in these cases.

摘要 1
誌謝 2
目錄 3
第一章 簡介 4
第二章 先前的研究 5
第三章 架構描述 6
第四章 針對架構設計的分析 7
第五章 模擬流程 8
第六章 實驗結果 9
第七章 結論與未來工作 10
英文附錄

[1] D. A. Patterson and J. L. Hennessy, Computer Architecture: A Quantitative Approach,
Second Edition. San Francisco, California: Morgan Kaufmann, 1996.
[2] L. B. Hostetler and B. Mirtich, \DLXsim: A simulator for DLX."
ftp://max.stanford.edu/pub/hennessy-patterson.software/, 1996.
[3] J. R. Larus, \SPIM S20: A MIPS R2000 simulator," Technical Report 90-966, Dept.
Computer Sci., Wisconsin Univ., 1990.
[4] R. F. Cmelik and D. Keppel, \Shade: A fast instruction-set simulator for execution
proling," in Proceedings of the 1994 ACM SIGMETRICS Conference onMeasurement
and Modeling of Computer Systems, May, 1994.
[5] D. Burger and T. M. Austin, \The SimpleScalar tool set, version 2.0," Technical Report
97-1342, Dept. Computer Sci., Wisconsin Univ., 1997.
[6] P. Grun, A. Halambi, A. Khare, V. Ganesh, N. Dutt, and A. Nicolau, \EXPRESSION:
A language for architecture exploration through compiler/simulator retargetability," in
Proc. Design, Automation and Test in Europe (DATE), 1999.
[7] A. Fauth, J. van Praet, and M. Freericks, \Describing instruction set processors using
nML," in Proc. European Design and Test Conf.(ED&TC), 1995.
[8] G. Hadjiyiannis, S. Hanono, and S. Devadas, \ISDL: An instruction set description
language for retargetability," in Proc. IEEE/ACM Design Automation Conf. (DAC),
pp. 299{302, 1997.
[9] S. Bashford, U. Bieker, B. Harking, R. Leupers, P. Marwedela, A. Neumann, and
D. Voggenauer, \The mimola language version 4.1," technical report, Dortmund Univ.,
1994.
[10] V. Kathail, M. Schlansker, and B. Rau, \HPL PlayDoh architecture specication: Ver-
sion 1.0," Technical Report HPL-93-80, HP Laboratories, 1994.
[11] S. Pees, A. Homann, V. Zivojnovic, and H. Meyr, \LISA machine description language
for cycle-accurate models of programmable DSP architectures," in Proc. IEEE/ACM
Design Automation Conf. (DAC), pp. 933{938, 1999.
[12] A. Homann, O. Schliebusch, A. Nohl, G. Braun, O. Wahlen, and H. Meyr, \A method-
ology for the design of application specic instruction set processors (ASIP) using the
machine description language LISA," in Proc. IEEE/ACM Int. Conf. Computer-Aided
Design (ICCAD), 2001.
[13] P. Grun, A. Halambi, A. Khare, V. Ganesh, N. Dutt, and A. Nicolau, \EXPRESSION:
An ADL for system level design exploration," Technical Report 1998-29, California
Univ., Irvine, Sep 1998.
[14] H. Tomiyama, A. Halambi, P. Grun, N. Dutti, and A. Nicolau, \Architecture description
languages for systems-on-chip design," in In Proc.Asian Pacic Conf. on Hardware
Description Languages (APCHDL), 1999.
[15] C. N. Fischer and J. R. J. LeBlanc, Crafting a compiler with C. Redwood, California:
The Benjamin/Coummings, 1991.
[16] L. L. Beck, Sytem Software: An Introduction to System Programming, Third Edtion.
Addison Wesley Longman, 1997.
[17] D. A. Patterson and J. L. Hennessy, Computer Organization & Design: the hard-
ware/software interface. San Francisco, California: Morgan Kaufmann, 1998.
[18] G. Kane and J. Heinrich, MIPS RISC Architecture. Prentice Hall, 1992.
[19] A. J. van de Goor, \Using march tests to test SRAMs," IEEE Design & Test of Com-
puters, vol. 10, pp. 8{14, Mar. 1993.
[20] C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, \A programmable
BIST core for embedded DRAM," IEEE Design & Test of Computers, vol. 16, pp. 59{70,
Jan.-Mar. 1999.
[21] R. Rajsuman, \Testing a system-on-a-chip with embedded microprocessor," in Proc.
Int. Test Conf. (ITC), pp. 499{508, 1999.

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