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研究生:李進福
研究生(外文):Jin-Fu Li
論文名稱:應用於系統晶片測試與診斷之有效方法
論文名稱(外文):Efficient Methodologies for Core-Based System-on-Chip Testing and Diagnostics
指導教授:吳誠文
指導教授(外文):Cheng-Wen Wu
學位類別:博士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:113
中文關鍵詞:系統晶片記憶體測試診斷內容定址記憶體資料壓縮階層式測試症狀內建自我測試
外文關鍵詞:system-on-chipmemory testingdiagnosisContent addressable memorydata compressionhierarchical testingsyndromebuilt-in self-test
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  • 收藏至我的研究室書目清單書目收藏:1
系統晶片(SOC)設計方法正逐漸成為積體電路設計工業的主流。為了減少設計時間,整合由多個來源的可重複使用核心(core)在系統晶片設計中是必要的。然而為了用合理的代價來設計與製造系統晶片,需要先克服很多挑戰,包含設計(design)、測試(test)及良率(yield)等問題。特別的是,在系統晶片中記憶體核心一般是最常被使用到的核心。也就是記憶體的面積一般佔據了一大部分的晶片面積並主宰此顆晶片的良率。因此診斷的技術在快速開發內嵌式記憶體(embedded memories)期間扮演非常重要的角色,它可用來捕捉設計與製造的錯誤及改善整體的良率與品質。由於昂貴與複雜的內嵌式記憶體錯誤分析過程及差的可存取性(accessibility),專研有效的診斷演算法就變的非常重要。在此論文中,我們介紹有效的系統晶片測試、記憶體測試及記憶體診斷技術。
在論文的第一部份,我們介紹一用於系統晶片的階層式測試方法。此方法可以支援IEEE P1500及1149.1封套的核心。一階層式測試管理器用來控制這些核心的測試過程被提出。一用來連接階層式管理器與記憶體內建自我測試(built-in self-test)電路的記憶體內建自我測試介面也被提出。因此內建自我測試電路可以經由串列式介面及平行式測試存取機制來控制。所提出的階層式測試控制方法有低面積及腳數負擔與高彈性的特色。一使用此方式的工業案例已經被實驗。實驗的結果顯示測試封套(test wrapper)與階層式控制電路的面積負擔約佔晶片面積的5.1%與0.63%。
在論文的第二部份,我們提出March為基礎的診斷演算法,這些演算法不僅可以偵測到錯誤單元的位置也可以分出錯誤的類別。用於bit-oriented及word-oriented記憶體之診斷演算法的複雜度分別為O(17N)及O((17+10B)N),這裡的N及B代表位址的數目及字元的長度。使用所提出之演算法,永駐錯誤(stuck-at faults)及耦合錯誤(coupling faults)之不同種類錯誤可以被區分出來。更進一步,耦合錯誤之加害者(aggressor)可以被找出。我們的word-oriented診斷演算法可以區分所有的字內(intra-word)及字間(inter-word)的耦合錯誤。所提出的診斷演算法有高診斷解析度及低複雜度的優點。
在論文的第三部份,兩個用於內容定址記憶體(Content Addressable Memories)的March-Like測試演算法首先被提出。除了典型的隨機存取記憶體(RAM)錯誤外,它們也可以偵測到內容定址記憶體特有的比較錯誤(comparison faults)。對於一NxW內容定址記憶體,第一個演算法需要9N讀/寫及2(N+W)比較來偵測所有的比較及隨機存取記憶體錯誤(但是無法完全偵測到字內耦合錯誤(intra-word coupling faults))。第二個演算法需要3Nlog2W寫及2Wlog2W比較來偵測還沒偵測到的字內耦合錯誤。與先前演算法比較,所提出的演算法有較高的錯誤涵蓋率(fault coverage)及較低的時間複雜度。更進一步,這兩個演算法可以測比較結果僅可由Hit或priority encoder輸出來觀察的內容定址記憶體。錯誤定位(Fault-location)演算法也被發展來定位有比較錯誤的cell。最後,一可根據不同的錯誤涵蓋率支援不同演算法的可規劃性的內建自我測試電路被提出。此設計的硬體負擔很低,對於一8Kx64位元的內容定址記憶體所需約2540個閘極。
在論文的第四部份,我們介紹兩個可使用來加速診斷資料從有支援診斷內建自我測試電路到外部測試機台間傳輸的資料壓縮技術。所提出的症狀累積技術(syndrome-accumulation)可壓縮錯誤細胞元位址與March症狀到原來大小的28%在使用March-17N診斷演算法前提下。此壓縮器的主要元件是一症狀累積電路,此電路可以用一內容定址記憶體來實現。實驗結果顯示對於一有164個錯誤1M位元的靜態隨機存取記憶體而言,硬體負擔僅大約佔0.9%。另一方面,一針對字元導向記憶體的樹狀壓縮技術也被提出。利用簡化的赫夫曼(Huffman)編碼技巧及分割每一256位元的漢明症狀(Hamming syndrome)為固定大小的符號,假設16位元的符號則所得到的平均壓縮比約為10。用來實現樹狀壓縮器所需增加的硬體負擔非常的小。所提出的壓縮技術能有效的降低記憶體診斷時間及測試機台的記憶體需求。
System-on-chip (SOC) design methodology is becoming the mainstream in the IC industry. Integrating reusable cores from multiple resources is essential in SOC design to reduce design time. To design and manufacture SOCs with reasonable cost, however, many challenges including design, test, and yield must be overcome. In particular, memory cores are most widely used cores in SOC designs. Thus memories usually represent a significant area of the chip and dominate the yield of the chip. Diagnosis technique plays a key role during the rapid development of the embedded memories, for catching the design and manufacturing failures and improving the overall yield and
quality. Investigation on efficient diagnosis algorithms is very important due to the expensive and complex fault/failure analysis process and low accessibility of embedded memories. In this thesis we present efficient techniques for SOC testing, memory testing, and memory diagnosis.
In the first part of this thesis, we present a hierarchical test methodology for SOC. It supports the IEEE P1500 and 1149.1 (JTAG) wrapped cores. A hierarchical test manager (HTM) is proposed to control the test process of these cores. A memory built-in self-test (BIST) interface is also presented, which connects the HTM and the memory BIST circuit. The BIST circuit can be controlled by the serial interface or the parallel test access mechanism (TAM). The proposed hierarchical test control scheme has low area and pin overhead, and high flexibility. An industrial case has been experimented using this scheme. The results show that the area overhead of the test wrappers and hierarchical test control circuitry are about 5.1% and 0.63%, respectively.
In the second part of this thesis, we propose March-based RAM diagnosis algorithms which not only locate faulty cells but also identify their types. The diagnosis complexity is O(17N) and O((17 + 10B)N) for bit-oriented and word-oriented diagnosis algorithms, respectively, where Nrepresents the address number and B is the data width. Using the proposed algorithms, stuck-at
faults, state coupling faults, idempotent coupling faults and inversion coupling faults can be distinguished. Furthermore, the coupled and coupling cells can be located in the memory array. Our word-oriented diagnosis algorithm can distinguish all of the inter-word and intra-word coupling faults, and locate the coupling cells of the intra-word inversion and idempotent coupling faults. With additional 2B-1 operations, the algorithm can further locate the intra-word state coupling
faults. With improved diagnostic resolution and test time, the proposed algorithms facilitate the development and manufacturing of semiconductor memories.
In the third part of this thesis, two efficient March-like test algorithms for Content Addressable Memories (CAMs) are proposed first. In addition to typical RAM faults, they also cover CAM specific comparison faults. The first algorithm requires 9N Read/Write operations and 2(N +W) Compare operations to cover comparison and RAM faults (but does not fully cover the intraword coupling faults), for an NxW-bit CAM. The second algorithm uses 3N log2W Write and 2Wlog2W Compare operations to cover the remaining intra-word coupling faults. Compared with the previous algorithms, the proposed algorithms have higher fault coverage and lower time complexity. Moreover, it can test the CAM even when its comparison result is observed only by the
Hit output or the priority encoder output. Fault-location algorithms are also developed for locating the cells with comparison faults. Finally, a programmable BIST circuit is proposed, which can be used for different test algorithms with various fault coverage requirements. It supports production
test as well as engineering/diagnostic test. Its hardware overhead is low─about 2,540 gates for an 8k64-bit CAM.
In the fourth part of this thesis, we present two data compression techniques that can be used to speed up the transmission of diagnostic data from the embedded RAM BIST circuit that has diagnostic support to external tester. The proposed syndrome-accumulation approach compresses the faulty-cell address and March syndrome to about 28% of the original size on average under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome accumulation circuit, which can be realized by a CAM. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. A tree-based compression technique for word-oriented memories is also presented. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size symbols, the average compression ratio is about 10, assuming 16-bit symbols. Also, the additional hardware to implement the treebased compressor is very small. The proposed compression techniques effectively reduce the memory diagnosis time as well as the tester storage requirement.
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 What Makes SOC Testing Different? . . . . . . . . . . . 2
1.3 SOC Test Challenges . . . . . . . . . . . . . . . . ..... 4
1.3.1 Core Test . . . . . . . . . . . . . . . . . . . . . . 4
1.3.2 Test Access and Isolation . . . . . . . . . . . . . . 5
1.3.3 Testing Interconnects and UDL . . . . . . . . . . . . . 6
1.3.4 Memory Yield Improvement . . . . . . . . . . . . . . . 7
1.3.5 Test Data Reduction . . . . . . . . . . . . . . . . . 9
1.3.6 Test Integration and Optimization . . . . . . . . . . 11
1.4 Research Goals . . . . . . . . . . . . . . . . . . . . . 15
1.5 Thesis Organization . . . .. . . . . . . . . . . . . . . 16
2 A Hierarchical Test Methodology for System-on-Chip 17
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . 17
2.2 IEEE P1500 Scalable Architecture . . . . . . . . . . . . 18
2.3 Test Wrapper Generation . . . . . . . . . . . . . . . . 20
2.3.1 Wrapper Cell Library . . . . . . . . . . . . . . . . . 20
2.3.2 Wrapper Instructions . . . . . . . . . . . . . . . . . 24
2.4 Hierarchical Test Scheme . . . . . . . . . . . . . . . . 25
2.4.1 Hierarchical Test . . . . . . . . . . . . . . . . . . 25
2.4.2 Hierarchical Test Manager . . . . . . . . . . . . . . 27
2.4.3 Wrapper Control Interface . . . . . . . . . . . . . . 30
2.4.4 Memory BIST Interface . . . . . . . . . . . . . . . . 31
2.4.5 Hardware and Test Reuse . . . . . . . . . . . . . . . 33
2.5 Experimental Results . . . . . .. . . . . . . . . . . . 35
2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . 39
3 March-Based RAM Diagnosis Algorithms for Stuck-At and Coupling Faults .............................................40
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . 40
3.2 Fault Models and Notation . .. . . . . . . . . . . . . 42
3.3 Diagnosis for Bit-Oriented RAMs . . . . . . . . . . . . 43
3.3.1 March Test . . . . . . . . . . . . . . . . . . . . . 43
3.3.2 March-17N Diagnosis Algorithm . . .. . . . . . . . . . 44
3.3.3 Locating the CF Aggressors . . . . . . . . . . . . . . 45
3.4 Diagnosis for Word-Oriented RAMs . . . . . . . . . . . . 48
3.4.1 Diagnosis with Two-phase Procedure . . . . . . . . . . 48
3.4.2 Locating the CFst(X) Aggressors . . . . . . . . . . . .51
3.5 Comparison and Discussion . . . . . . . . . . . . . . . 54
3.6 Summary . .. . . . . . . . . . . . . . . . . . . . . . . 58
4 Testing and Diagnosing Embedded Content Addressable Memories
...........................................................59
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . 59
4.2 CAM Architecture . . . . . . . . . . . . . . . . . . . . 61
4.3 Functional Fault Models . . . . . . . . . . . . . . . . 62
4.4 Test Algorithms . . .. . . . . . . . . . . . . . . . . . 64
4.5 Diagnostic Algorithms . .. . . . . . . . . . . . . . . . 68
4.6 Programmable BIST . . . . . . . . . . . . . . . . . . . 69
4.7 Experimental Results . . . . . . . . . . . . . . . . . 74
4.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . 76
5 Diagnostic Data Compression Techniques for EmbeddedMemories
with Built-In Self-Test ...................................78
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . 78
5.2 Memory BIST with Diagnostic Support . . . . . . . . . . 80
5.3 Compression by Syndrome Accumulation . . . . . . . . . . 81
5.3.1 Syndrome Accumulation Process . . . . . . . . .. . . . 81
5.3.2 Syndrome Accumulation Circuit . . . . . . . . . . . . 83
5.4 Tree-Based Compression Approach . . . . . . . . . . . .. 85
5.4.1 Huffman Coding Technique . . . . . . . .. . . . . . . 86
5.4.2 Tree-Based Coding Technique . . .. . . . . . . . . . . 87
5.4.3 Hamming Syndrome Compression . . . . . . . . . . . . . 88
5.4.4 Syndrome Compressor Design . . . . . . . . . . . . . 90
5.5 Experimental Results and Analysis . . .. . . . . . . . . 93
5.5.1 Results for Syndrome Accumulation . . . . . . . . . . 93
5.5.2 Results for Tree-Based Compression Scheme . . . . . . 95
5.6 Summary . . . . . . . . . .. . . . . . . . . . . . . . . 97
6 Conclusions and Future Work ...............................99
6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . 99
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . 101
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