臺灣博碩士論文加值系統

摘 要
浮動閘極之氮化處理應用於非揮發性記憶體元件，可以改善氧化層的品質與其可靠度。浮動閘極之氮化處理使用NH3和N2O 退火之後在沉積一層化學氣相沉積的二氧化矽在加N2O快速退火。使用這個處理將會呈現出很優良的電特性。附帶一提，多晶矽閘極用同時參雜磷同時成長閘極的方式會有比較好的特性。這個製程的結構可以提供現階段快取記憶體與電子寫入抹除之可程式記憶體對於增進氧化層特性的一個參考。

`In this thesis, nitridation on floating gate of nonvolatile memory devices is used to improve tunneling oxide quality and reliability. Samples, nitridized by NH3 with additional N2O annealing on poly-oxynitride (poly I) and then deposited with a CVD TEOS and a post deposition RTA N2O annealing, show excellent electrical properties in term of electric breakdown field, charge to breakdown, low electron trapping rate, and reliability characteristics. In addition, the CVD TEOS oxide deposited on the phosphorus in-situ doped polysilicon nitrided with NH3 and followed with an N2O RTA treatment shows better performance inter-dielectric than control samples. This structure is a very promise for the interpoly dielectric of EEPROM and flash memory devices.

CONTENTS
ABSTRACT I
ACKNOWLEDGEMENTS II
CONTENTS III
LIST OF FIGURES VI
CHAPTER 1
Introduction 1
CHAPTER 2
The Organizations of This Research 3
2-1 Oxide Integrity Measurement 3
2-1-1 Basic I-V characteristics 3
2-1-2 Measuring Time-Dependent Breakdown Behavior 5
2-1-3 Mathematics of Reliability Characteristics 7
2-2 Gated-Control Diode Measurement 9
2-3 Hot Carrier Effect Measurement 13
CHAPTER 3
Interpoly-Oxynitride Grown by NH3 Nitridation and N2O RTA Treatment
3-1 Experimental
3-2 Results and Discussion 23
3-2-1 The Electrical Characteristics of J-E Curves 23
3-2-2 Material Analyses 24
3-2-3 Electron Trapping Characteristics 24
3-2-4 Characteristics of Charge to Breakdown 24
3-3 Summary 25
CHAPTER 4
Impact of Tunneling Oxide for Nitridation on
Floating Gate
4-1 Experimental
4-2 Results and Discussion
4-2-1 The Electrical Characteristics of J-E Curves 32
4-2-2 Electron Trapping Characteristics 33
4-2-3 Characteristics of Charge to Breakdown 33
4-2-4 Gated-Diode Measurement 33
4-2-5 Hot Carrier Effect Measurement 34
4-3 Summary 35
CHAPTER 5
Conclusion 49
REFERENCES 50

[1] C. S. Lai, T. F. Lei, and C. L. Lee, “ The Characteristics of polysilicon oxide grown in pure N2O,” IEEE Trans. Electron Devices, Vol. 43, pp.326-331, Feb. 1996.
[2] C. H. Kao, C. S. Lai, and C. L. Lee, “ The TEOS oxide deposited on phosphorus in-situ/POCl3 doped polysilicon with rapid thermal annealing in N2O ,” IEEE Trans. Electron Devices, Vol. 45, pp.1927-1933, Sept. 1998.
[3] T. F. Lei et al., “Characterization of polysilicon oxides thermally grown and deposited on the polished polysilicon films ,” IEEE Trans. Electron Devices, Vol. 45, pp.921-917, 1998.
[4] S. C. Song et al., “Ultra thin high quality stack nitride/oxide gate dielectrics prepared by in-situ rapid thermal N2O oxidation of NH3-nitride Si,” in VLSI Tech. Symp. Dig., 1999, pp.137-138.
[5] T. M. Pan, T. F. Lei, and T. S. Chao, “Robust ultra-thin oxynitride dielectrics by NH3 nitridation and N2O RTA treatment,” IEEE Electron Devices Lett., Vol. 21, pp.378-380, Feb. 2000.
[6] T. M. Pan, T. F. Lei, W. L Yang, and T. S. Chao, “High quality interpoly-oxynitride grown by NH3 nitridation and N2O RTA treatment,” IEEE Electron Devices Lett., Vol. 22, pp68-70, NO. 2, Feb. 2001.
[7] J. W. Lee, C. L. Lee, T. F. Lei, and C. S. Lai, “High reliability polyoxide fabricated by using TEOS oxide deposited on disilane polysilicon film,” IEEE Trans. Electron Devices, Vol. 48, NO. 4 pp.743-749, Apr. 2001.
[8] W. L. Yang, T. S. Chao, C. M. Cheng, T. M. Pan, and T. F. Lei, ”High quality interpoly dielectrics deposited on the nitrided-polysilicon for nonvolatile memory devices,” IEEE Trans. Electron Devices, Vol. 48, NO. 7 pp.1304-1309, July 2001.
[9] C. Y. Lin, C. Y. Chang, and C. C. H. Hsu, “Suppression of boron penetration in BF2-implanted p-type gate MOSFET by trapping of Fluorines in amorphous gate,” IEEE Trans. Electron Devices, Vol. 42, NO. 8 pp.1503-1509, Aug. 2001.
[10] A. S. Grove and D. J. Fitzgerald,” Surface effects on p-n junctions: characteristics of surface space-charge regions under non-equilibrium conditions,” Solid-State Electron., vol. 9, p. 783, 1966.
[11] J. H. Klootwijk, M. H. H. Weusthof, H. van Kranenburg, P. H. Worelee, and H. Wallinga, ”Improvements of deposited inter-polysilicon dielectric characteristics with RTP N2O anneal,” IEEE Electron Devices Lett., Vol. 17, pp. 358-359, 1996.
[12] S. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1981.
[13] A. S. Grove, Physics and Technology of Semiconductor Devices, John Wiley & Sons, Inc. 1967
[14] Deter K. Schroder, Semiconductor Material and Device
Characterization, 2nd, John Wiley & Sons, Inc. 1998
[15] T. F. Lei, J. Y. Cheng, S. Y. Shiau, T. S. Chao, and C. S. Lai, ” Improvement of polysilicon oxide by growing on polished film,” IEEE Electron Devices Lett., Vol. 18, NO.6 pp. 270-271, June 1997.
[16] C. H. Kao, C. S. Lai, and C. L. Lee, “ The TEOS CVD oxide deposited on phosphorus In-situ doped polysilicon with rapid thermal annealing,” IEEE Electron Devices Lett., Vol. 44, NO.11 pp. 526-528, Nov. 1997.
[17] M. C. Jun, Y. S. Kim, and M. K. Han, ”Polycrystalline silicon oxidation method improving surface roughness at the oxide/polycrystalline silicon interface,” Appl. Phys. Lett., vol. 66, no. 17, p.2206, 1995
[18] C. Y. Chang, H. Y. Lin, T. F. Lei, J. Y. Cheng, L. P. Chen, and B. T. Dai, “Fabrication of thin-film transistors by chemical mechanical polished polycrystalline silicon films,” IEEE Electron Devices Lett., Vol. 17, pp. 100, 1996.
[19] T. Ono, T. Mori, T. Ajioka, and T. Takayashiki, “Studies of thin poly-si oxides for E and E2PROM,” in IEDM Tech. Dig., pp.380-383 1985
[20] T. F. Lei, J. H. Chen, M. F. Wang, and T. S. Chao, “Characteristics of polysilicon oxides combining N2O nitridation and CMP process,” IEEE Trans. Electron Devices, Vol. 47, NO. 8 pp. 1545-1552, Jan. 1997.
[21] S. L. Wu, C. Y. Chen, T. Y. Lin, C. L. Lee, T. F. Lei, and M. S. Liang, “Investigation of the polarity asymmetry on the electrical characteristics of thin polyoxides grown on n+ polysilicon,” IEEE Trans. Electron Devices, Vol. 44, NO. 1 pp. 153-159, Jan. 1997.
[22] H. J. Cho, C. S. Kang, K. Onishi, S. Gopalan, R. Nieh, R. Choi, E. Dharmarajan, and J. C. Lee, “Novel Nitrogen Profile engineering for Improved TaN-HfO2-Si MOSFET Performance,” in IEDM Tech. Dig., pp. 655-658, 2001.
[23] H. Hwang, W. Ting, D. L. Kwong, and J. Lee, ”Electrical and reliability characteristics of ultrathin oxynitride dielectric prepared by rapid thermal processing in N2O,” in IEDM Tech. Dig., pp. 421-424, 1990.
[24] J. C. Lee, and C. Hu, “Polarity asymmetry of oxides grown on polycrystalline silicon ,” IEEE Trans. Electron Devices , Vol. 35, pp. 1063-1070, 1988.
[25] S. L. Wu, C. L. Lee, and T. F. Lei, “Characteristics of ultrathin oxide prepared by low-temperature wafer loading and nitrogen preannealing before oxidation,” J. Appl. Phys. Vol. 72 pp. 1378-1385, 1992.
[26] E. Avni, O. Abramson, Y. Sonnenblick, and J. Shappir, “ Charge trapping in oxide grown on polycrystalline silicon layers,” J. Electrochem. Soc. , vol.135, pp.182-186, 1988.
[27] L. Faraone, “Thermal SiO2 films on n+ polycrystalline silicon: Electrical conduction and breakdown,” IEEE Trans. Electron Devices , Vol. ED-33, pp. 1785-1794, 1986.