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研究生:曾培哲
研究生(外文):PEI-JER TZENG
論文名稱:次微米金氧半元件之電漿充電效應
論文名稱(外文):Plasma Charging Effects on Sub-micron MOS Devices
指導教授:張廖貴術
指導教授(外文):Kuei-Shu Chang-Liao
學位類別:博士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學門:工程學門
學類:核子工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:116
中文關鍵詞:電漿蝕刻氮化氧化層高介電係數電漿充電效應閘極介電層
外文關鍵詞:plasma etchingoxynitridehigh dielectric constantplasma charging effectgate dielectric
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由於元件縮小化、電漿不均勻性、以及高介電係數閘極介電層的考量,使得電漿充電所致損害依然是金氧半元件製程中的關鍵課題。首先,氧化層厚度的縮小至其電流傳導機制為直接穿隧(direct tunneling)時,其電漿充電所致損傷可能會減輕。再者,利用並聯二極體(shunt diode)於閘極上,可測得電漿不均勻所致的充電極性:在高密度電漿機台中,晶圓中心附近呈現正電荷累積;反之,晶圓邊緣則呈現負電荷累積。另外,閃動雜訊(flicker noise)能有效地反映出電漿充電損害所導致之界面陷阱(interface trap)情形:界面陷阱的增加會增大所測得之閃動雜訊。最後,元件蝕刻後,將其額外暴露於純電漿中,可大幅減輕因電漿蝕刻製程所導致的元件電特性率退現象。在減低電漿充電效應方面,相較於傳統的氮化氧化層,利用兩階段氮化處理(two-step nitridation)之氮化氧化層,搭配非晶矽閘電極(amorphous silicon),能更有效地減低電漿充電導致之電特性及可靠度衰退情形:其原因在於非晶矽閘電極有助於界面應力的紓解,以及第二階段氮化處理可減低有害元素的擴散至閘極氧化層。在高介電係數閘極介電層(Si3N4 , Ta2O5)之電漿充電效應方面,堆疊(stacked)的閘極結構在低電場之下的較低閘極漏電流特性雖可歸因於緩衝層(buffer layer)的介入,但其電漿充電效應之下的電性衰退並未明顯改善,且其終究受限於元件厚度的縮小化;而在單層(single layer)的閘極結構方面,氮化矽(Si3N4)閘極介電層因其漏電較大且其元件之崩潰時間太短,而暴露其可靠度的問題;而五氧化二鉭(Ta2O5)閘極介電層因其電流傳導機制與陷阱(trap)有極大關係,因而較厚之五氧化二鉭薄膜對電漿充電所致損傷較敏感。

Plasma charging induced damage on gate dielectrics of MOS devices is an important issue in terms of shrinking dimension, plasma non-uniformity and effects on high-k gate dielectrics. A comprehensive study of plasma charging effects on the electrical properties of MOS devices was investigated in this thesis. Scaling effect of gate oxide thickness shows that the electrical property degradation induced by plasma charging damage may be slight as gate oxide thickness scales down into direct tunneling regime. For high-frequency application, the 1/f noise was found to be a promising index for assessing plasma charging damage. Extra exposure to plasma ambient can greatly reduce the plasma charging induced damage, which can be attributed to photo-annealing. For reinforcing the robustness of gate dielectrics, gate oxynitride formed by two-step nitridation was demonstrated to have better electrical reliability as compared to the conventional one-step nitridation, especially accompanied by amorphous silicon gate electrode. This improvement could be attributed to the relaxation of interfacial strain by amorphous silicon gate electrode and the suppression of hydrogen effects by gate oxynitride using two-step nitridation. For alternative gate dielectric in the future application, plasma-charging damage on Si3N4 and Ta2O5 gate dielectrics with high dielectric constant was also investigated. In the stacked gate dielectrics, such as Ta2O5/oxynitride and Ta2O5/Si3N4, the mixed effect of the buffer layer (oxynitride or Si3N4) and Ta2O5 film works well in low electrical field region. Yet it doesn’t show any significant reduction in plasma charging induced electrical degradation and eventually limits the thickness scaling. For MOS devices with Si3N4 gate dielectric, the leakier characteristic and shorter time to breakdown reveal its inferior reliability. For MOS devices with Ta2O5 gate dielectric, the trap-assisted current mechanism makes a thicker physical thickness of Ta2O5 film more susceptible to plasma charging induced damage.

Abstract (in English)
Abstract (in Chinese)
Acknowledgment
Contents
Table Captions
Figure Captions
Chapter 1
Introduction
1.1 Mechanism for Plasma Charging Damage
1.1.1 Causes for Plasma Charging Effects
1.1.2 A Physical Model for Plasma Charging Effect
1.1.2.1 DC Effect
1.1.2.2 AC Effect
1.2 Outline of this thesis
Chapter 2
Experiments and Measurements
2.1 The Process Flow
2.1.1 MOS Devices with SiO2-based Gate Dielectrics
2.1.2 MOS Devices with High-k Gate Dielectrics
2.2 The Antenna Test Structure for Plasma Charging Effects
2.3 Dry Etching System with High Density Plasma
2.4 Characterization Methods
2.4.1 TDDB Method
2.4.2 Hot Carrier Stress
2.4.3 F-N Stress
Chapter 3
Plasma Charging Damage on Thin Gate Oxide
3.1 Introduction
3.2 Results and Discussions
3.2.1 Scaling effects on plasma charging damage
3.2.2 The relationship between flicker noise and plasma charging effect
3.2.3 Shunt diode and charging polarity
3.2.4 Extra plasma exposure
3.3 Summary
Chapter 4
Reduction of Plasma Charging Damage by Gate Process
4.1 Introduction
4.2 Results and Discussions
4.2.1 Reduction of Plasma Charging Induced Reliability Degradation by Gate Oxynitride Process
4.2.2 Reduction of Plasma Charging Induced Reliability Degradation by Two-step Nitridation on Gate Oxynitride
4.2.3 Effects of Amorphous Silicon as Gate Electrode on Plasma Charging Induced Reliability Degradation
4.3 Summary
Chapter 5
Plasma Process Induced Damage on MOS Capacitors with High-k Gate Dielectrics
5.1 Introduction
5.2 Plasma Charging Damage during Etching and Photoresist Ashing
5.3 Fabrication of the Gate Dielectrics and Dielectric Constant Extraction
5.3.1 Oxynitride Formation
5.3.2 Si3N4 Deposition
5.3.3 Ta2O5 Deposition
5.3.4 Ta2O5/oxynitride Deposition
5.3.5 Ta2O5/Si3N4 Deposition
5.3.6 Gate Dielectric Constant Extraction
5.4 Results and Discussions
5.4.1 Plasma Charging Induced Damage in Etching Process
5.4.2 Plasma Charging Induced Damage in Photoresist Ashing Process
5.4.3 Plasma Charging Effect Induced Non-uniformity in Gate Current
5.4.4 Gate Current at High Electrical Field
5.4.5 Time to Breakdown and Electrical Breakdown Field
5.5 Summary
Chapter 6
Conclusions and Suggestions
6.1 Conclusions
6.2 Suggestions on Future Work
Reference

[1] S. Fang and J. P. McVittie, “Charging damage to gate oxides in an O2 magnetron plasma,” J. Appl. Phys., Vol. 72, p. 4865, 1992.
[2] S. Murakawa, S. Fang, and J. P. McVittie, “Surface charging effects on etching profiles,” IEDM Tech. Dig., 1992, p.57.
[3] S. Fang and J. P. McVittie, “Oxide damage from plasma charging breakdown mechanism and oxide quality,” IEEE Trans. Electron Devices, Vol. 41, p.1034, 1994.
[4] C. T. Gabriel, “Gate oxide damage from polysilicon etching,” J. Vac. Sci. Tech., B, Vol. 9, p.370, 1991.
[5] W. M. Greene, J. B. Kruger, and G. Kooi, “Magnetron etching of polysilicon: etching damage,” J. Vac. Sci. Tech., B, Vol. 9, p.366, 1991.
[6] C. Gabriel, S. Bothra, Milin, and T. Herbst, “Plasma process-induced charging through contacts and vias,” Proc. of VMIC, 1995, p. 394.
[7] B. Y. Tsui, S. H. Liu, G. Lih, J. H. Ho, C. H. Chang, and C. Y. Lu, “Recovery phenomenon and local filed sensitivity on wafer charge-up effect of magnetically enhanced reactive ion etch system,” IEEE Electron Device Lett., Vol. 16, p.64, 1995.
[8] S. Fang, S. Murakawa, J. P. McVittie, “Modeling of oxide breakdown from gate charging during resist ashing,“ IEEE Trans. Electron Devices, vol. 10, p.1848, 1994.
[9] H. J. Tao et al, “Impacts of etcher chamber design on plasma induced devices damage for advanced oxide etching,” 3rd International Symp. on PPID, 1998, p.60.
[10] K. Hashimoto et al, “Reduction of the charging damage from electron shading effect,” Appl. Phys. Lett., Vol.62, p.1507, 1993.
[11] K. Noguchi et al, “Reliability of thin gate oxide under plasma charging caused by antenna topography-dependent electron shading effect,” IEDM Tech. Dig., 1997, p.441.
[12] B. Chapman, “Glow Discharge Processes,” John Wiley & Sons Inc., 1980.
[13] K. P. Cheung and C. P. Chang, “Plasma-charging damage: a physical model,” J. Appl. Phys., Vol.75, p.4415, 1994.
[14] M. Alavis et al, “Effect of MOS devices scaling on process-induced gate charging”, 2nd International Symp. on PPID, 1997, p.7.
[15] C. Hu, J. Zhao, G. P. Li, P. Liu, E. Worley, J. White, and R. Kjar, "The effect of plasma etching induced gate oxide degradation on MOSFET’s 1/f noise," IEEE Electron Device Lett., vol. 16, p.61, 1995.
[16] W. K. Chim, B. P. Yeo, P. S. Lim and D. S. H. Chan, "Low-frequency noise characterization of latent damage in thin oxides subjected to high-field impulse stressing," IEEE Electron Device Lett., vol. 19, p.363, 1998.
[17] K. Lai et. al., “Effects of oxide exposure, photoresist and dopant activation on the plasma damage immunity of ultrathin oxides and oxynitrides,” IEDM Tech. Dig., 1995, p.319.
[18] S. V. Hattangady, R. Kraft, D.T, Grider, M.A. Douglas, G. A. Brown, P. A. Tiner, J. W. Kuehne, P. E. Nicollian, and M. F. Pas, “Ultrathin nitrogen-profile engineered gate dielectric films,” IEDM Tech. Dig., 1996, p.495.
[19] B. Maiti, P. J. Tobin, V. Misra, R. I. Hegde, K. G. Reid, and C. Gelatos, “High performance 20Å NO oxynitride for gate dielectric in deep sub-quarter mircon CMOS technology,” IEDM Tech. Dig., 1997, p.651.
[20] K. S. Chang-Liao and L. C. Chen, “Physical and electrical properties in metal-oxide-Si capacitors with various gate electrodes and gate oxides,” J. Vac. Sci. Technol. B, Vol. 15, p.942, 1997.
[21] K. S. Chang-Liao and J. M. Ku, “ Improvement of oxynitride reliability by two-step N2O nitridation,” Solid-State Electronics, vol.43, p.2057, 1999.
[22] D. Park and C. Hu, “ Plasma charging damage on ultrathin gate oxides,” IEEE Electron Device Lett., vol. 19, p.1, 1998.
[23] H. Iwai and H. S. Momose, “Ultra-thin gate oxides-performance and reliability,“ IEDM Tech. Dig., 1998, p.163.
[24] T. P. Ma, “Making silicon nitride a viable gate dielectric,” IEEE Trans. Electron Devices, vol. 45, p.680, 1998.
[25] H. F. Luan, S. J. Lee, C. H. Lee, S. C. Song, Y. L. Mao, Y. Senzaki, D. Robert and D. L. Kwong, “High quality Ta2O5 gate dielectrics with Tox.eq<10Å,“ IEDM Tech. Dig., 1999, p.141.
[26] Y. C. Yeo, Q. Lu, W. C. Lee, T. J. King, C. Hu, X. Wang, X. Guo, and T. P. Ma, “Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric” IEEE Electron Device Lett., vol. 21, p. 540, 2000.
[27] Hyungsuk Jung, Kiju Im, Dooyoung Yang, and Hyunsang Hwang, “Electrical and reliability characteristics of an ultrathin TaOxNy gate dielectric prepared by ND3 annealing of Ta2O5,” IEEE Electron Device Lett., vol. 21, p.563, 2000.
[28] S. Ma, “Prediction of plasma charging induced gate oxide tunneling current and antenna dependence”, 1st International Symp. on PPID, 1996, p.20.
[29] J. P. McVittie, “Plasma charging damage: An overview”, 1st International Symp. on PPID, 1996, p.7.
[30] M. A. Lieberman et al, “Principles of plasma discharges and materials processing”, John Wiley & Sons, 1994.
[31] O. A. Popov, “High density plasma sources,” Noyes Publications, 1995.
[32] K. Eriguchi, Y. Uraoka, H. Nakagawa, T. Tamaki, M. Kubota, and N. Nomura, “Quantitative evaluation of gate oxide damage during plasma processing using antenna-structure capacitors,” Jpn. J. Appl. Phys., Vol. 33, p.83, 1994.
[33] L. K. Han, M. Bhat, D. Wristers, J. Fulford, and D. L. Kwong, “Polarity dependence of dielectric breakdown in scaled SiO2,” IEDM Tech. Dig., 1994, p.617.
[34] K. R. Mistry, B. J. Fishbein, and B. S. Doyle, “Effect of plasma-induced charging damage on n-channel and p-channel MOSFET hot carrier reliability,” Proc. of IRPS, 1994, p.42.
[35] K. Noguchi, and K. Okumura, “The effect of plasma-induced oxide and interface degradation on hot carrier reliability,” Proc. of IRPS, 1994, p.232.
[36] S. Wolf, “Silicon processing for the VLSI era, Vol.3,” Lattice Press, p.573, 1995.
[37] K. Tamabe et al, “Degradation of silicon dioxide film under high electric field stress”, 1st International Symp. on PPID, 1996, p.243.
[38] B. Prince, “Semiconductor Memories,” John Wiley & Sons, p.609, 1991.
[39] E. Cartier, “Characterization of the hot-electron-induced degradation in the thin SiO2 gate oxides”, Microelectronics and Reliability, Vol.38, p.201, 1998.
[40] H. S. Momose et al, “Study of the manufacturing feasibility of 1.5nm direct-tunneling gate oxides”, IEEE Electron Device Lett., Vol.45, p.691, 1998.
[41] T. Gu et al., “Impact of polysilicon dry etching on 0.5 μm NMOS transistor performance: the presence of both plasma bombardment damage and plasma charging damage,” IEEE Electron Device Lett., vol. 15, p. 48, 1994
[42] S. Wolf, “Silicon processing for the VLSI era, Vol.3,” Lattice Press, p.436, 1995.
[43] K. S. Chang-Liao et al, “MOS capacitor hot electron and radiation hardness improvement by combination of gate electron deposited using amorphous Si and gate oxides rapid thermal annealed in N2O,” Jpn. J. Appl. Phys., Vol.36, p.604, 1997.
[44] Y. Okayama et al, “Nitrogen incorporation optimization for down-scaled CMOSFET with N2O based oxynitride process,” Int. Symp. on VLSI Tech., 1998, p.220.
[45] C. Hu et al., “Hot-electron-induced MOSFET degradation — model, monitor, and improvement,” IEEE Trans. Electron Devices, Vol. 32, p.375, 1985.
[46] W. Ting, H. Hwang, J. Lee, D.L. Kwong, “Composition and growth Kinetics of ultrathin SiO2 films formed by oxidizing Si substrate in N2O,” Appl. Phys. Lett., Vol. 57, p.2808 , 1990
[47] R. P. Vasquez and A. Madhukar, ”Strain-dependent defect formation kinetics and a correlation between flatband voltage and nitrogen distribution in thermally nitrided SiOxNy/Si structures,” Appl. Phys. Lett., Vol. 47, p.998, 1985.
[48] A. Pacelli et al, “Effect of N2O nitridation on the electrical properties of MOS gate oxides”, Microelectronic and Reliability, Vol. 38, p.239, 1998.
[49] K. S. Chang-Liao and J. M. Ku, “Improvement of oxynitride reliability by two-step N2O nitridation,” Solid-State Electronics, vol.43, p.2057, 1999.
[50] S. Wolf, “Silicon Processing for the VLSI era, Vol. 3,” Lattice Press, p.513, 1995.
[51] S. Fang and J. P. McVittie, “Model for oxide damage gate charging during magnetron etching,” Appl. Phys. Lett., Vol.62, p.1507, 1993.
[52] T. Hori et al., “Electrical and physical properties of ultrathin reoxidized nitrided oxides prepared by rapid thermal processing,” IEEE Trans. Electron Devices, vol.36, p.340, 1989.
[53] T. Hori, “Inversion layer mobility under high normal field in nitrided-oxide MOSFET’s,” IEEE Trans. Electron Devices, vol. 37, p. 2058, 1990.
[54] B. Yu et al., “Gate engineering for deep-submicron CMOS transistors,” IEEE Trans. Electron Devices, vol. 45, p. 1253, 1998.

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1. 83. 蔡志方,2000,〈論地方自治處分之行政救濟〉,《律師雜誌》,第244期,第56-61頁。
2. 94. 羅傳賢,1998,〈行政聽證程序法制與民權保障〉,《經社法制論叢》,第6期,第248-267頁。
3. 84. 蔡茂寅,1999,〈地方制度法之特色與若干商榷〉,《律師雜誌》,第244期,第39-55頁。
4. 77. 趙永茂,1999,〈台灣縣市政府的自治監督及其檢討〉,《政治科學論叢》,第11期,第21-46頁。
5. 96. 蘇俊斌,2000,〈美國法院與公共政策〉,《空大行政學報》,第10期,第231-247頁。
6. 74. 湯德宗,1999,〈論行政程序的正當程序〉,《月旦法學雜誌》,第55期,第152-168頁。
7. 70. 楊桂杰,1994,〈立法院建立聽證制度之研究〉,《立法院院聞》,第22卷第8期,第69-80頁。
8. 66. 黃志弘,1998a,〈由成文法精神探討都市設計審議制度行政行為〉,中華民國建築學會,《建築學報》,第25期,第105-111頁。
9. 65. 游伯欽,1997,〈美國聯邦法院對「正當法律程序」之解釋理論〉,《立法院院聞》,第25卷第2期,第43-62頁。
10. 62. 張劍寒,1975,〈行政程序法中聽證制度之研究〉,《憲政思潮》,第31期,第18-39頁。
11. 47. 高孟定,1994,〈都市計畫的本質〉,《逢甲學報》,第27期,第373-390頁。。
12. 10. 史慶璞,1999,〈政府行政行為與美國行政爭訟制度之研究〉,《輔仁法學》,第18期,第45-63頁。
13. 1. 林山田,1999,〈論正當法律程序原則〉,《軍法專刊》,第45卷第4期,第1-7頁。
14. 9. 史慶璞,1993,〈美國國家環境政策之制定、執行與司法監督〉,《輔仁法學》,第12期,第95-109頁,。
15. 8. 巨克毅,1994,〈當代社會正義理論之研究〉,《國立中興大學共同學科期刊》,第3期,第255-276頁,。