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研究生:陳榮昇
研究生(外文):Jung-Sheng Chen
論文名稱:低雜訊X光偵檢器前端讀出電路之設計
論文名稱(外文):Low-Noise X-Ray Detector Readout Front- End Design
指導教授:周懷樸
指導教授(外文):Hwai-Pwu Chou
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學門:工程學門
學類:核子工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:78
中文關鍵詞:低雜訊讀出電路電荷靈敏放大器
外文關鍵詞:low noisereadout circuitcharge sensitive amplifier
相關次數:
  • 被引用被引用:1
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本研究是利用折疊串接式(folded-cascode)放大器的高增益和高頻寬與高雜訊抵抗力的特點,與波形整形放大器串接,形成一偵檢器前端讀出電路且適用於X-ray多通道偵檢器分析系統,並適用於個人可攜性微型偵檢器系統。並採用國內台灣積體電路 TSMC 0.35μm SPQM製程技術,設計一個3V單電壓,偵檢器電容為30pF,增益為255 mV/fC、功率消耗為520μW,並針對電荷靈敏放大器的輸入元件MOSFET 進行最佳化設計,最佳化結果為通道寬度W=725μm和通道長度L=0.7μm可以來得到最小的等效雜訊電荷(ENC)<600 e-,波形整形放大器則利用簡單的微分與積分形成帶通濾波器,用來改善信號雜訊比,整體偵檢器前端讀出電路具有低雜訊和低消耗功率的優點,整體晶片面積為480×420μm2,並探討整體系統的操作電壓、溫度與製程變動的靈敏度變化,整體系統的操作電壓可容忍10%的變化誤差,操作溫度為0∼70℃均可正常工作,操作速度可達0.5MHz。
The purpose of the work is to design an integrated amplifier system to use with silicon photodiodes for soft X-ray counting. The amount of charge generated in silicon diodes from soft X-rays is very low and therefore, a low noise design is a major concern in this study. Moreover, for portable and miniature dosimeter applications, the circuit is to be powered by a single supply voltage and requires low power consumption.
The amplifier circuit consists of a charge sensitive amplifier (CSA) and a pulse shaping circuit. Both stages are based on a folded cascode operational trans-conductance amplifier (OTA) structure for noise reduction and a better frequency response. In the CSA section, the channel length of the frond end transistor M0 is optimized for noise based on a nominal detector capacitance 30pF. The feedback capacitor 0.3pF is used to reduce detector capacitance variations by the Miller effect. That the ENC of the front end section is less than 600 electrons. The pulse shaping circuit is a CR-RC filter. The operating frequency is set about 0.5 MHz and the CR and RC time constants are set about 1μs for high counting applications. To facilitate batch production, all passive components are integrated in the same chip using the 0.35 SPQM process. The overall chip size is about 480 μm x 420 μm and is dominated by the coupling capacitor C1.
The width and length parameters of each MOS component used in the amplifier were iterated to optimize amplification factor and power consumption. The overall gain of the amplifier stage is about 255 mV/fC in the interested frequency range around 0.5 MHz. The IC manufacturing process has a threshold voltage about 0.6 volt for PMOS and NMOS components. The DC level of the output signal is set about 0.6 volt. Using a power supply of 3 volts, the maximum signal swing is about 0.6 volt and the total power consumption is less than 520μW. The design has passed the “four corner” analyses; sensitivity analyses were also performed for operating temperature variations from 0 to 70 ℃ and a 10% supply voltage fluctuation. An IC chip has been manufactured and the preliminary test showed a satisfactory result.
誌謝 Ⅰ
Abstract Ⅱ
摘要 Ⅲ
目錄 Ⅳ
圖目錄 Ⅶ
表目錄 Ⅹ
第一章 緒論 1
1.1 研究動機 1
1.2 文獻回顧 2
1.2.1 偵檢器 3
1.2.2 前置放大器 3
1.2.3 波形整形放大器 5
1.3 一般小電流訊號讀出電路之比較 6
1.4 研究目的 8
第二章 偵檢器前端讀出電路設計原理 9
2.1 偵檢器前端讀出電路之雜訊分析 9
2.1.1 MOSFET的熱雜訊分析 9
2.1.2 MOSFET的閃爍雜訊分析 10
2.2 偵檢器前端讀出電路之ENC推導 11
2.3 電荷靈敏放大器設計原理 16
2.4 波形整形放大器設計原理 19
2.5 偵檢器前端讀電路全級設計 20
第三章 偵檢器前端讀出電路設計與模擬 21
3.1 ENCd的模擬與最佳化 21
3.1.1 模擬與最佳化 21
3.1.2 ENCd受製程變化的影響 25
3.2 電荷靈敏放大器之設計 27
3.2.1 轉導放大器設計 27
3.2.2 電荷靈敏放大器設計 30
3.2.3 電荷靈敏放大器靈敏度分析 34
3.3 波形整形放大器之設計 38
3.3.1 波形整形放大器電路 38
3.3.2 波形整形放大器靈敏度分析 40
3.4 偵檢器前端讀出電路全級電路 42
3.4.1 線性偵檢器前端讀電路全級特性分析 42
3.4.2 波形整形放大器的時間常數 43
3.4.3 線性偵檢器前端讀出電路靈敏度分析 45
第四章 偵檢器前端讀出電路之靈敏度分析 49
4.1 非線性偵檢器前端讀出電路特性分析 49
4.1.1 非線性偵檢器前端讀出電路特性分析 49
4.1.2 非線性前端讀出電路靈敏度分析 50
4.1.3 線性與非線性偵檢器前端電路之比較 55
4.2 元件尺寸和臨界電壓變動之分析 56
4.3 設計結果比較 58
4.4 波形整形放大器之改良比較 60
4.5 偵檢器前端讀出電路晶片系統測試考量 63
第五章 結論與建議 66
5.1 結論 66
5.2 建議 68
參考文獻 70
附錄A ENC matlab程式說明 74
附錄B 電路佈局圖 75
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