臺灣博碩士論文加值系統

由於網際網路的多元化，通訊及多媒體的蓬勃發展，使得數位訊號處理的需求也日益增多。相對於更快速和更便宜的處理晶片將被大量的使用。而DCT(Discrete Cosine Transfer)剛好符合這樣的條件，從眾多的演算法中脫穎而出。
本設計是採用省面積的New ROM-basic Look-up Table(以記憶體為主的新查表法)架構的8點1_D DCT為基礎，只需加法器、移位器及存放已知cos係數的唯讀記憶體形成累加器(Rom Accumulation，
RAC)就可完成1_D DCT的運算，架構上非常簡單。我們也比較一些其他常用實現DCT運算的方式，確實我們的設計在面積及成本上有所改進。
在配合實現兩個控制器去控制2_D RAM及3_D RAM的讀與寫可擴充成三維運算，控制整個1_D、2_D、3_D DCT的運算流程。用兩個控制器的原因是為了提高硬體的效能，當我們只做2_D 運算時就不須啟動第二個控制器以減少功率的消耗及控制器上設計可以較為簡單，使得實現時較不會有複雜的繞線且時序上不容易出錯，最後加上一多工器去選擇所要的運算結果形成一顆多維的處理晶片

誌謝 I
摘要 II
目錄 III
圖目錄 V
表目錄 VIII
第一章 前言 1
1.1簡介 1
1.2 研究動機 4
第二章 文獻回顧 6
2.1 DCT/IDCT基本演算法 6
2.1.1 1_D DCT/IDCT基本演算法 6
2.1.1.1 選用DCT_2 的原因 9
2.1.2 2_D DCT/IDCT基本演算法 12
2.1.3 3_D DCT/IDCT基本演算法 12
2.2 1_D DCT硬體架構之比較 14
2.2.1 直接計算演算法 14
2.2.2 列行矩陣查表法 16
2.2.3 共享乘法器演算法 19
2.2.4 以記憶體為主的新查表法 21
2.3 2_D DCT硬體架構之比較 23
2.3.1 串接型 23
2.3.2 合併型 24
第三章 硬體架構 28
3.1 1_D DCT/IDCT硬體實現及考量 28
3.2 2_D DCT/IDCT硬體實現及考量 33
3.3 3_D DCT/IDCT硬體實現及考量 36
第四章 測試與分析結果 43
4.1 測試方法與分析品質計算 43
4.2 1_D DCT/IDCT 測試與模擬結果 46
4.3 2_D DCT/IDCT 測試與模擬結果 47
4.4 3_D DCT/IDCT 測試與模擬結果 48
第五章 結論與建議 49
5.1 結論 49
5.2 建議 51
參考文獻 52
附錄A 共享乘法器演算法公式推導 54
附錄B 佈局圖及接腳配置 57

[1]V.Oppenheim and W.Schafer,”DISCRETE-TIME SIGNAL PROCESSING”,second edition。
[2]Micheal John Sebastian Smith,”Application Specific Integrated Circuits”, 1997.
[3]K. Madisetti ,”VLSI Digital Signal Processors-An introduction to rapid prototyping and sesign synthesis”, 1995.
[4]K.C.Chang,”Digital Systems Design eith VHDL and Synthesis:An integrated Approach”,1999.
[5]Andrew Rushton,”VHDL for Logic Synthesis”second edition,1998.
[6]Nell H.E. Weste, Kamran Eshraghlan,”Principles of CMOS VLSI Design:A systems Perspective 2/E”.
[7]蕭如宣，”VHDL 數位系統電路設計”,儒林,2000
[8]林傳生，”使用VHDL電路設計語言之數位電路設計”,儒林,1998
[9]Douglas L.Perry，譯:林嘉興，”完整的VHDL使用指引”
,McGraw-Hill,2000.
[10]Jan M. Rabaey,”Digital Integrated Circuits”,Prentice Hall,1996.
[11]Lars Wanhammar,”DSP Integrated Circuits”,Academic Press,1999.
[12]William B. Pennebaker, Joan L. Mitchell.”JPEG still image data compression standard”New York :/Van Nostrand Reinhold,/1992.
[13] D. Slawecki and W. Li,”DCT/IDCT processor design for high data rate image coding”, IEEE Trans. Circuits Syst. Video Technol,vol.2, pp135-146, June 1992.
[14] S . Uramoto etal ,”A 100 MHz 2-D discrete cosine transform core processor”,IEEE J. Solid-State Circuits,vol. 27,pp.492-499,Apr.1992.
[15] Wei-chun,Yimu Fan,Kenneth W.Hsu,”An 8*8 Discrete Cosine Transform Model Using VHDL”, ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International , 1992 ,Page(s): 339 —344.
[16] Y. P. Lee,M. J. Chen,L. G. Chen,C. W. Ku,“A Cost-Effective Architecture for 8*8 Two-Dimensional DCT/IDCT Using Direct Method” Circuits and Systems for Video Technology, IEEE Transactions on , Volume: 7 Issue: 3 , June 1997 ,Page(s): 459 —467.
[17]T. S. Chang,C. S. Kung,C. W. Jen,”A Simple Processor Core Design for DCT/IDCT” Circuits and Systems for Video Technology, IEEE Transactions on , Volume: 10 Issue: 3 , April 2000 ,Page(s): 439 —447.
[18]A. Madisetti and A. N. Willson,”A100 Mhz 2-D 8*8 DCT/IDCT processor for HDTV Applicstions”,IEEE Trans. Circuits Syst.Video Technol,vol.5,pp-158-165,Apr.1995.
[19]W. H. Chen, C.H Smith and S.C Fralick,”Fast computation algorithm for the discrete cosinetransform”,IEEE.Traans.Commun.,vol.COM-25,
pp1004-1009,sep.1977.
[20]N. I. Cho, and S. U. Lee,”Fast Algorithm nad Implementation of 2-D Discrete Cosine Transform”,IEEE TRANSACTION ON CIRCUITS AND SYSTEM,vol.38,NO.3,MARCH 1991.
[21]C. L. Wang,and C. Y. Chen,”High-Throughput VLSI Architectures for the 1-D and 2-D Discrete Cosine Transforms”,IEEE TRANSAC-
TIONS ON CITCUIT AND SYSTEMS FOR VIDEO TECHNOLO-
GY,vol.5,NO.1,Feb,1995.
[22]P. Duhamel and C. Guillemot,”Polynomial transform computation of 2-D DCT”,in Proc. ICASSP’90, Apr. 1990,pp.1515-1518.
[23]J. H. Hsiao, L. G. Chen, T. D. Chiueh, and C. T. Chen,”High throughput CORDIC-basic systolic array design for the Discrete Cosine Transform”,IEEE Trans. Circuits Syst. Video Technol, vol.5,pp.218-224,
June 1995.
[24]Jalloh,A.Aggoun and M.McCormick,”A 3D DCT ARCHITECTURE FOR COMPRESSION OF INTEGRAL 3D IMAGES”.
[25]Marc Servais,Gerhard De Jager,”Video Compression using the Three Dimensional Discrete Cosine Transforms(3D-DCT)”,Communications and Signal Processing, 1997. COMSIG '97., Proceedings of the 1997 South African Symposium on , 1997.
[26]Raymond K.W.Chan and M.C.Lee,”3D-DCT Quantization as a compression Technique for Video Sequences”,Virtual Systems and MultiMedia, 1997. VSMM '97. Proceedings., International Conference on , 1997 Page(s): 188 —196.