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研究生:林孟勇
研究生(外文):Meng-Yong Lin
論文名稱:脈衝信號峰值取樣與保持電路設計
論文名稱(外文):Pulse Signal Peak Detector Sample and Hold Circuit Design
指導教授:周懷樸
指導教授(外文):Hwai-Pwu Chou
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學門:工程學門
學類:核子工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:80
中文關鍵詞:峰值檢測取樣保持臨界鑑別器
外文關鍵詞:Peak detectsampleholdDiscriminator
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峰值檢測電路(Peak detect sample and hold:PDSH)普遍存在電壓降(Voltage Droop)和超越電位(Overshoot Voltage)的問題,本文主要採用CMOS元件,針對 PDSH電路,探討各部位元件的工作區間,以及電路轉移曲線的偏壓操作情形,然後加以改進,讓PDSH電路在追隨模式(Trace Mode)和保持模式(Hold Mode)時,能夠解決存在電壓降的問題和超越電位的改善。另外設計一個臨界鑑別器( Threshold Discriminator Circuit)用做為PDSH和ADC電路的控制介面,一方面可以用來讓PDSH搭配ADC電路做輸入的控制,判斷電路對輸入接受訊號的開始與隔離;另一方面設定雜訊的門檻電位,用來避免偵檢到雜訊訊號的輸入,也因此不再考慮基底電位(Pedestal Voltage)的存在的問題。最後本文的電路,採用台積電TSMC 0.351p4m的製程,3V的單電壓源,模擬改進之後,完全改善電壓降的問題,並且超越電位低於2.5mV以下。
Peak detection and sample-hold (PDSH) circuitry commonly exists voltage droop, pedestal, and overshoot problems. In this work, a PDSH architecture is invented which is operated with a 3V singled voltage and implemented using the TSMC 0.35 micron 1p4m CMOS process.
Comparing with previous circuits, we have improved the operational characteristics and the bias condition to prevent voltage droop and overshoot problems when the PDSH circuit is operated in the trace mode and hold mode. Besides, we designed a discriminator circuit to interface the PDSH with an ADC. This circuit can distinguish the input signal from noise; meanwhile, it serves as an input control for the PDSH circuit to avoid the pedestal voltage problem. Simulation results indicated that the PDSH circuit has no voltage droop and pedestal; voltage overshoot is less than 2.5 mV.
第一章 緒論………………………………………………………1
第二章 文獻回顧…………………………………………..……..4
2.1 時序(Clock)控制取樣及保持電路…………...…………..4
2.2 OP控制與時序控制電路的不同………………..………..11
2.3峰值檢測的操作…………………………………....……..14
2.4 BJT峰值檢測電路……………….………………………..15
2.5 CMOS峰值檢測電路…………………………….……….17
2.5.1峰值檢測電路…………………………….…..……18
2.5.2非理想操作的討論…………………………...……21
第三章 脈衝峰值檢測器的設計考量……………………………..24
3.1 基本峰值檢測器之操作…………………………….……24
3.2 放大器元件………………….…………..…….………….28
3.3 電流鏡元件……….……………………...…….……...….30
3.4 重置開關元件……….……………………….……..…….36
3.4.1增強型MOS負載反相器…………………………39
3.4.2 CMOS反相器………………………….…..…...…41
3.5 電源的供應……….…………………..………………….44
3.6 電路的實現……….…………………..………………….45
第四章 控制器電路的設計………………..…………………...…52
4.1控制器電路……………………...…………...………...…52
4.2電路的設計…………………...……………….………….54
4.3 電路的實現…………………..…………………...…...…57
第五章 結果與討論……………..……………………..…….....…61
5.1 串接前級的模擬………………..………..…………...…61
5.2 頻率響應分析……………..………..………………...…62
5.3 靈敏度分析……………..……………..……………...…65
5.4晶片實現與量測………..………….………….……....…68
第六章 結論與建議……………..………….………….……....…71
6.1 總結……………..………………….…………….…...…71
6.2 建議…………….…..………………….………….…...…72
參考文獻……………..………………….……………...……...…73
附錄A(其他PDSH電路比較)…….…………………………….75
[1] M. W. Kruikamp and D.M. Leenaerts, “A CMOS Peak Dectect Sample and Hold Circuit”, IEEE Trans. On Nucl. Science, Vol.41, (1)295-298(1994).
[2] Jieh-Tsorng Wu, “IEE 6736 Analog Integrated Circuits (II)
-- Spring 2002 --,” National Chiao-Tung University Department of Electronics Engineering.
[3] Werner Haas and Peter Dullenkopf, “A Novel Amplitude and Time Detector for Narrow Pulse Signals,” IEEE Trans. On Instrumentation and Measurement, vol. IM-35, NO. 4, DEC 1986.
[4] Erhard Keppler, Albrecht Glasmachers, and Wolfgang Winkelnkemper, “New Design Aspects for an Energetic Particle Telescope for Space Missions”, IEEE Trans. On Instrmentation and Measurement, Vol. IM-30,NO. 3,September 1981.
[5] Shu-Yuan Chin; Chung-Yu Wu, “A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources ”, IEEE Journal of Solid-State Circuit, vol. 29, pp.1374-1380, Nov. 1994.
[6] M. N. Ericson and M. L. Simpson, “A Low-Power, CMOS Peak Detect and Hold Circuit for Nuclear”, IEEE Trans. On Nucl. Science, Vol.42,(4)724-728(1995).
[7] D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley and Sons, Inc.,1997.
[8] Phillip E. Allen and Douglas R.Holberg, CMOS Analog Circuit Design Second Edition, Oxford University Press, Inc., 2002.
[9] P. J. Lim and B. A. Wooley, “A High-Speed Sample-and-Hold Technique Using a Miller Hold Capacitance,” IEEE Journal of Solid-State Circuit, vol. 26, pp.643-651, APRIL 1991.
[10] C. Fiorini, A. Pullia, E. Gatti, A. Longoni and W. Butter, “Amonlithic implementation of a switched-current Wheel amplifier for multi channel Silicon Drift Detector,” IEEE Trans. On Nucl. Science, Vol.46, NO. 3, JUNE 1999.
[11] Pierre F. Buckens and Michael S. Veatch, “A High Performance Peak Detect & Hold Circuit for Pulse Height Analysis,” IEEE Trans. On Nucl. Science, Vol.39, NO. 4, JUNE 1992.
[12] Paul R. Grey, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer, Analysis and Design of Analog Integrated Circuit 4th, John Wiley and Sons, Inc.,2001.
[13] Jan M. Rabaey, Degital Integrated Circuit : A Design Perspective, Prentice Hall, Inc., 1996.
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