跳到主要內容

臺灣博碩士論文加值系統

(3.238.252.196) 您好!臺灣時間:2022/08/13 22:42
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:許嘉倫
研究生(外文):Chia-Lung Hsu
論文名稱:低壓化學氣相沈積法配合快速熱處理對閘極氮氧化層電特性之影響
論文名稱(外文):Electrical Properties of Gate N/O layer formed by LPCVD with N2O RTP
指導教授:王天戈張廖貴術
指導教授(外文):Tien-Ko WangKuei-Shu Chang-Liao
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學門:工程學門
學類:核子工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:103
中文關鍵詞:低壓化學氣相沈積閘極氮氧化層快速熱處理
外文關鍵詞:GateLPCVDRTP
相關次數:
  • 被引用被引用:0
  • 點閱點閱:92
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本論文在探討以不同氧化階段次數但總氧化時間相同的氧化條件,對金氮半( MNS,Metal Nitride Semiconductor )元件特性的影響。同時也對MNS元件的特性對薄膜厚度( 25Å、30 Å和35 Å )的依存性,作一有系統的探討。最後,探討不同的氧化條件對抑制銅擴散的比較,其中,亦對退火溫度( 未經退火、300℃、350℃和400℃ )之選擇作驗證及討論。
在探討不同氧化條件及不同階段的氧化處理中,實驗結果顯示,元件經過900℃兩次的快速熱處理後,在電特性上,有較佳的表現。而在探討MNS特性對氮化矽薄膜的依存性中,我們發現最薄的元件(25Å),在漏電流、Ditm、Vfb及Ebd方面都有最佳表現;尤其是經過900℃兩次快速熱處理的樣本。在抑制銅擴散方面,900℃兩次快速熱處理的樣本有較佳的表現;而退火溫度,則是以300℃最佳。

第一章 序論
1.1 序言
1.2 各章摘要
1.3 氧化氮化矽層改善元件的特性的機制
1.3.1 RTP通N2O氧化氮化矽層之反應機制
1.3.2 氧原子鑽入Si3N4/Si界面對元件的影響
1.4 研究目的
1.5 文獻回顧
1.5.1 N2O/NO成長之氮氧化層
1.5.2 氮離子佈植後成長之氮氧化層
1.5.3 噴射氣相沈積(JVD)的氮化矽層
1.5.4 以化學氣相沈積(CVD)成長的氮化矽層
第二章 多階段RTP對金氮半元件特性之影響
2.1 研究緣由與目的
2.2 主要的實驗設備
2.2.1 低壓化學氣相沈積(LPCVD)
2.2.2 快速熱處理(RTP)系統
2.3元件的製程與分析
2.3.1 元件的製作
2.3.2 元件的分析
2.4 結果與討論
2.4.1 氧化氮化矽層中各原子的縱深分佈及化學組態
2.4.2 MNS元件的初始特性
2.4.3 MNS元件的抗熱電子特性
2.5 結論
第三章 氮化矽層厚度對金氮半元件特性之影響
3.1 研究的緣由與目的
3.2 元件的製程
3.3 結果與討論
3.3.1 MNS元件的初始特性
3.3.2 MNS元件的抗熱電子特性
3.4 結論
第四章 氮化矽層對抑制銅擴散之探討
4.1 研究的緣由與目的
4.2 元件的製程
4.3 結果與討論
4.4 結論
第五章 結論與建議
5.1結論
5.2建議
參考文獻

(1) Allan, A.; Edenfeld, D.; Joyner, W.H., Jr.; Kahng, A.B.; Rodgers, M.; Zorian, Y.," 2001 technology roadmap for semiconductors ",Computer , Volume: 35 Issue: 1 , Jan. 2002
(2) Ma, T.P. ," Making silicon nitride film a viable gate dielectric ",Electron Devices, IEEE Transactions on , Volume: 45 Issue: 3 , March 1998 ,Page(s): 680 -690
(3) Kim, B.Y.; Luan, H.F.; Kwong, D.L.," Ultra thin (<3 nm) high quality nitride/oxide stack gate dielectrics fabricated by in-situ rapid thermal processing",Electron Devices Meeting, 1997. Technical Digest., International , 1997 ,Page(s): 463 -466
(4) Liu, C.T.; Ma, Y.; Becerro, J.; Nakahara, S.; Eaglesham, D.J.; Hillenius, S.J.," Light nitrogen implant for preparing thin-gate oxides ",IEEE Electron Device Letters , Volume: 18 Issue: 3 , March 1997,Page(s): 105 -107
(5) Ying Shi; Xiewen Wang; Tso-Ping Ma," Electrical properties of high-quality ultrathin nitride/oxide stack dielectrics",Electron Devices, IEEE Transactions on , Volume: 46 Issue: 2 , Feb. 1999 ,Page(s): 362 —368
(6) J. Ahn, W. Ting, and D.L. Kwong, ”Furnace Nitridation of Thermal SiO2 in Pure N2O Ambiemt for VLSI MOS Application” ,IEEE Electron Device Letter, Vol. 13, p.177, 1992.
(7) H. Hwang, W. Ting, D.L. Kwong and J. Lee, in IEDM Tech. Dig, p. 421, 1990.
(8) Y. H. Lin, C.S. Lai, C.L. Lee, T.F. Lei and T.S. Chao, IEEE ED-43, p. 1161, 1996.
(9) L.K. Han, S. Crowder, M. Hargrove, E. Wu, S.H. Lo, F. Guarin, E. Grabbe and L. Su,IEDM Tech.Dig., P. 643, 1997.
(10) Feng Wensiu, Chen Pusheng, Huang Shiping, “Study on Oxygen Distribution and Oxided Mechanism for Ultrathin Oxided Si3N4 by Rapid Thermal Oxidation”, IEEE, 1996.
(11) K. Ando, K. Hamano, A. Ishitani, “Ultrathin Sillicon Nitride Films Prepared by Combining Rapid Thermal Nitridation with Low-Pressure Chemical Vapor Deposition”, IEEE, 1991.
(12) S. M. Sze, ”Current Transport and Maximum Dielectric Strength of Silicon Nitride Films,” J. Appl. Phys. 1967.
(13) E. Suzuki and Y. Hayashi, ”Carrier Conduction and Trapping in Metal-Nitride-Oxide-Semiconductor Structure,” J. Appl. Phys. 1982.
(14) D. V. Tsu, G. Lucovsky, and M. J. Mantini, ”Local Atomic Structure in Thin Films of Silicon Nitride and Silicon Dioxide Produced by Remote Plasma-Enhanced Chemical-Vapor Deposition,” Phys. Rev. ,1986.
(15) K. Kobayashi, A. Teramoto, and M. Hirayama, “Charge Transport in Ultrathin Silicon Nitrides,” J. Electrochem.Soc., 1995.
(16) P. C. Fazan, et al., IEEE Electron Device Lett.Vol.11 , P 279, 1990.
(17) G. Q. Lo, et al., IEEE Electron Device Lett. 13, P 372, 1992.
(18) K. Ando, et al., Sympo. VLSI Tech. Dig. , P 47, 1993.
(19) W. Ting, G. Q. Lo, J. Ahn, T. Y. Chu, and D. L. Kwong, “ MOS Characteristics of Ultrathin SiO2 Prepared by Oxidizing Si in N2O “, IEEE Electron Device Lett., vol. 12 , pp. 416-418 , Aug. 1991.
(20) R. M. Patrikar, R. Lai,and J. Vasi, “ Interface State Generation due to High-Field Stressing in MOS Oxides “, Solid-State Electron., vol. 38 , no. 32 , pp. 477-480 , 1995.
(21) G. W. Yoon, A. B. Joshi, J. Kim, and D. L. Kwong, “MOS Characteristics of NH3-Nitrided N2O-Grown Oxides “, IEEE Electron Device Lett., vol. 14 , pp. 179-181 , Apr. 1993.
(22) H. Fukuda, M. Yasuda, T. Iwabuchi, and S. Ohno, “ Novel N2O-Oxinitridation Trchnology for Forming Highly Reliable Eeprom TunnelOxide Films “, IEEE Electron Device Lett., Vol. 12 , pp. 587-589 , Nov. 1991.
(23) J. Ahn, W. Ting, and D. L. Kwong, “ Furnace Nitridation of Thermal SiO2 in Pure N2O Ambient for ULSI MOS Applications “, IEEE Electron Device Lett., Vol. 13 , pp. 117-179 , Feb. 1992.
(24) W. Ting, G. Q. Lo, J. Ahn, T. Chu, and D. L. Kwong “, Coparison of Dielectric Wear-Out between Oxides Grown in O2 and N2O “, in Proc.IEEE Reliab. Phys Symp., p. 323-326 , 1991.
(25) G. J. Dunn and S. A. Scott, “ Channel Hot-Carrier Stressing of Reoxidized Nitrided Silicon Dioxide “, IEEE Trans. Electron Devices, Vol. 37, pp.1719-1726, July 1990.
(26) T. Hori, H. Iwasaki , and K. Tsuji, “ Electrical and Physical Properticsof Ultrathin Reoxidized Nirtrided Oxides Prepared by Rapid Thermal Processing “, IEEE Trans. Electron Devices, Vol.36, pp. 340-350, Feb. 1989.
(27) T. Y. Chu, W. Ting, J. H. Ahn, S. Lin, and D. L. Kwong, “ Study of The Composition of Thin Dielectrics Grown on Si in a Pure N2O Ambient “, Appl. Phys. Lett., Vol. 59, pp. 1412-1414, 1991.
(28) M.N. Kim, K. Lim, M.H. Boe, S.H. Kang, Y.G. Yoo, ” Breakdown Phenomena in MIS Structure” , Proc. of the 3rd Int’l Conf. on Properties and Applications of Dielectric Materials, p.164, 1991.
(29) S. C. Song, H.F. Luan, Y.Y. Chen, M. Gardner, J. Fulford, M. Allen,” Ultrathin (≦20Å)CVD Si3N4 Gate Dielectric for Deep-Sub-Micron CMOS Devices “, IEDM, p. 373-376, 1998.
(30) P. C. Fazan, et al., IEEE Electron Device Lett.Vol.11 , P 279, 1990.
(31) G. Q. Lo, et al., IEEE Electron Device Lett. 13, P 372, 1992.
(32) K. Ando, et al., Sympo. VLSI Tech. Dig. , P 47, 1993.
(33) P. Bornhauser and G. Calzaferri, Spectrochim. Acta, Part A, 46(1990)1045
(34) Bauer, A.J.; Mayer, P.; Frey, L.; Haublein, V.; Ryssel, H. ”Forming nitrided gate oxides by nitrogen implantation into the substrate before gate oxidation by RTO”,Ion Implantation Technology Proceedings, 1998 International Conference on page: 26 - 29 vol.1 22-26 June 1998
(35) D. C. Edelstein, june 27-29, 1995 VMIC Conference
(36) D. C. Edelstein, J. Heidenreich, R. Goldblatt, and J. Slattery, IEEE IEDM, (1997)
(37) J. D. McBrayer, R. M. Swanson, and T. W. Sigmon, Electrochem. Soc. Solid-State Science and Technology, Vol. 133, No. 6, pp. 1242 (1986)
(38) L. A. Clevenger, N. A. Bojarczuk, and L. Stolt, J. Appl. Phys., Vol. 73, pp. 300 (1993)
(39) M. T. Wang, Y. C. Lin, and M. C. Chen, J. Electrichem. Soc., Vol. 145, No. 7, pp. 2538 (1998)
(40) Tung Ming Pan,Tan Fu Lei,Huang Chun Wen, and Tien Sheng Chao “Characterization of Ultrathin Oxynitride (18—21 A) Gate Dielectrics by NH3 Nitridation and N2O RTA Treatment”,IEEE Transactions on Electron Devices, Vol. 48, No. 5, May 2001
(41) W. H. Lin, K. L. Pey, Z. Dong, S. Y.-M. Choi, M. S. Zhou, T. C. Ang,C. H. Ang, W. S. Lau, and J. H. Ye,”Effects of Post-Deposition Anneal on the Electrical Properties of Si3N4 Gate Dielectric”,IEEE Electron Device Letters, Vol. 23, No. 3, March 2002
(42) Quazi D. M. Khosru, A. Nakajima, T. Yoshimoto, and S. Yokoyama,” Low Thermal-Budget Ultrathin NH3-Annealed Atomic-Layer-Deposited Si-Nitride /SiO2 Stack Gate Dielectrics With Excellent Reliability”,IEEE Electron Device Letters, Vol. 23, No. 4, April 2002 page:179
(43) M. S. Angyal and Y. Shacham-Diamand, Appl. Phys. Lett., Vol. 67, pp. 2152 (1995)
(44) Yider Wu, Yi-Mu Lee, and Gerald Lucovsky,” 1.6 nm Oxide Equivalent Gate Dielectrics Using Nitride/Oxide (N/O) Composites Prepared by RPECVD/Oxidation Process”, IEEE Electron Device Letters, Vol.21, No. 3, March 2000 page:116
(45) Hanyang Yang, Hiro Niimi, Jeff W. Keister, Gerald Lucovsky, and Jack E. Rowe,” The Effects of Interfacial Sub-Oxide Transition Regions and Monolayer Level Nitridation on Tunneling Currents in Silicon Devices”, IEEE Electron Device Letters, Vol. 21, No. 2, February 2000 page 76
(46) Alvin L. S. Loke, Changsup Ryu, Patrick Yue, James S. H. Cho, and S. Simon Wong, IEEE Electron Device Letters, Vol. 17, No. 12, p. 549 (1996)
(47) H. C. Chan, Member, “ Trapping, Conduction, and Dielectric Breakdown in Si3N4 Films on As-Deposited Rugged Polysilicon “, IEEE Electron Device Letters, Vol. 12, No 9,1991.
(48) 汪建民主編, “材料分析”, 中國材料科學學會, 1998初版
(49) 莊達人主編, “VLSI製造技術”, 高立圖書有限公司, 1997五版

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top