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研究生:胡義奐
論文名稱:以DSP模組實現全數位鎖相迴路應用於水下QPSK系統之載波回復
論文名稱(外文):Implementation of an All Digital Phase-locked Loop for QPSK Carrier Recovery Using DSP Module
指導教授:呂福生
學位類別:碩士
校院名稱:國立海洋大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
中文關鍵詞:載波回復全數位式鎖相迴路水下無線通訊
外文關鍵詞:carrier recoveryall digital phase-locked loopUW wireless communication
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無線通訊因為收發端相對運動與通道效應的影響,傳送訊號易受都卜勒效應,造成接收訊號在頻率與相位上變動,傳統方法乃利用鎖相迴路控制接收端產生弦波的相位與頻率,達成載波回復的目的。
近年DSP技術發展成熟且數位化系統具有很多優點,故本論文採用TMS320C6711 DSK數位訊號處理器發展模組,實現一應用於QPSK載波回復的全數位式鎖相迴路,其可追蹤$ m \displaystyle{\frac{ i}{4}}$內的相位差,使接收端產生弦波與接收訊號載波相匹配,此外本論文利用實驗水槽搭配自製數位至類比轉換器和SONY SIR-1000W記錄器,將真實環境的接收訊號,引入系統做離線分析,以驗證鎖相迴路之正確性與載波回覆之實用性;由實驗可知,結合鎖相迴路的QPSK接收器,在水槽環境下,可有效克服通道對於相位變動的影響,降低因相位變動而驟升之錯誤率目的。

In wireless communication, the transmitted signal was affected by channel and Doppler effect. So that the phase and frequency of the received signal are randomly varied. In conventional receiver, carrier recovery is conducted by controlling the frequency and phase of the voltage controlled oscillator (VCO) in the phase-locked loop. Digital processing system has many advantages, using the TMS320C6711 DSK, an all digital phase-locked loop (ADPLL) for QPSK carrier recovery is constructed in this thesis. A frequency offset estimator is also included in the ADPLL to enhance the performance. It can minimize the phase error fast and make the carriers of received signal and local oscillator match each other. Furthermore, the D/A converter and SONY SIR 1000W data recorder are used to process the transmitted signal for off-line analysis. The experimental results show that the QPSK receiver using phase-locked loop is effective to overcome the phase drift problem, and reduce the BER caused by suddenly phase variation.

1 緒論
1.1 前言與研究動機 . . . . . . .. . . . . . . . . . . . . . . 1
1.2 研究目的. . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 本論文各章節要點概述. . . . . . . . . . . . . . . . . . . 3
2 水下聲傳通訊環境與數位載波回復機制
2.1 水下聲波通道. . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 水下聲波特性. . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 水下聲波模型. . . . . . . . . . . . . . . . . . . . . . 6
2.2 載波回復機制. . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1 平方律迴路. . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2 柯斯塔迴路. . . . . . . . . . . . . . . . . . . . . . . 8
2.2.3 重複調變法. . . . . . . . . . . . . . . . . . . . . . . 9
2.3 數位訊號處理器. . . . . . . . . . . . . . . . . . . . . . 10
2.3.1 TMS320C6711 DSK 簡介. . . . . . . . . . . . . . . . . . 11
2.3.2 系統軟體發展. . . . . . . . . . . . . . . . . . . . . . 11
2.3.3 外部記憶體介面(external memery interface, EMIF) . . . . 13
3 全數位鎖相迴路之設計
3.1 通訊系統簡介. . . . . . . . . . . . . . . . . . . . . . . 15
3.2 鎖相迴路設計. . . . . . . . . . . . . . . . . . . . . . . 16
3.2.1 相位偵測器. . . . . . . . . . . . . . . . . . . . . . . 17
3.2.2 壓控震盪器. . . . . . . . . . . . . . . . . . . . . . . 18
3.2.3 迴路濾波器. . . . . . . . . . . . . . . . . . . . . . . 20
3.3 數位鎖相迴路系統. . . . . . . . . . . . . . . . . . . . . 22
4 水下QPSK系統載波回復之實現
4.1 系統硬體架構. . . . . . . . . . . . . . . . . . . . . . . 26
4.1.1 D/A轉換器 . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.2 SONY SIR-1000W. . . . . . . . . . . . . . . . . . . . . 28
4.2 系統軟體發展. . . . . . . . . . . . . . . . . . . . . . . 28
4.3 水槽通道測試實驗. . . . . . . . . . . . . . . . . . . . . 31
5 結論與未來展望

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[2] J. G. Proakis, Digital Communciation, Charpter 14,1995.
[3] T. H. Eggen, A. B. Baggeroer, and J. C. Preisig, "Communciation over doppler spread channels part I:channel and receiver presentation," IEEE Journal of Oceanic Engineering, Vol.25, No.1, Jan. 2000
[4] G. L. Do, and K. Feher, "An ultra-fast carrier recovery versus traditional synchronizers," IEEE Trans. On Broadcasting, vol. 42, no. 1, March 1996
[5] Texas Instruments, "TMS320C6000 CPU and instruction set reference guide," TI Literature Number:SPRU189C, February, 2001.
[6] Texas Instruments, " TMS320C6000 optimizing C compiler user's guide," TI Literature Number:SPRU1871, April, 2001.
[7] Texas Instruments, "TMS320C6000 peripherals reference guide, " TI Literature Number:SPRU190D, Feb. 2001.
[8] T. S. Rappaport Wireless Communciations, Principles and Practice, Prentice-Hall, 1996
[9] S. Hinedi, and W. C. Lindsey, "Intersymbol interference eects on BPSK and QPSK carrier tracking loops," IEEE Trans. On Communications, vol. 38, no. 10, pp. 1670-1676, October 1990.
[10] "Survey of digital phase-locked loops," IEEE On Proc., vol. 69, pp. 410-431, Apr. 1981.
[11] N.-G. Kim, and I.-J. Ha, "Design of ADPLL for both large lock-in range and good tracking performance," IEEE Trans. On Circuits and Systems, vol. 46, no. 9, Sep. 1999.
[12] Analog Devices, "Quad 8-bit voltage out CMOS DAC vomplete with internal 10V reference," Datasheet-DAC8426
[13] O. Yaniv, and D. Raphaeli, "Near-optimal PLL design for decisionfeedback carrier and timing recovery," IEEE Trans. On Communications, vol. 49, no. 9, Sep. 2001.
[14] 陳信宏,王逸如, "數位信號處理的新利器 TMS320C6X," 全華科技圖書股份有限公司, 2000。
[15] 陳彥良, "應用DSP實現π/4DQPSK直序展頻式水下聲傳數據機," 國立臺灣海洋大學電機工程研究所碩士論文, 88.6。

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