臺灣博碩士論文加值系統

摘 要
本論文敘述了一個全積體化CMOS鎖相迴路設計，其可使用來設計一個頻率合成器在無線通訊接收端和發射端電路當本地震盪器使用。
以鎖相迴路為基礎之頻率合成器包含了一個除96的除頻器、此除頻器是由一個主從式高頻預除器及一個除48的除頻器所組成，還有一個無突波輸出的相位/頻率偵測器，一個電荷充放電路，一個使用二階低通濾波器的迴路濾波器，以及一個LC-tank壓控震盪器其輸出頻率之可調頻範圍為2.28到2.42 GHz。相位/頻率偵測器電路用於偵測參考訊號與迴授訊號之相位與頻率差，然後輸出UP和DN訊號。而電荷幫浦及迴路濾波器電路則將PFD輸出的數位訊號轉換為一個類比電壓訊號以控制壓控震盪器的輸出頻率。除頻電路則使用一個主從式架構電路及同步與非同步電路來做成一個除96的除頻器。
所有電路是以TSPC 0.25 1P5M的CMOS模型來設計，整體電路的消耗功率為52.3 mW。整個晶片面積為1701 ×1365 μm2。

Abstract
This paper describes the design of a fully integrated 2.4 GHz CMOS phase-locked loop intended for use as the frequency synthesizer for local oscillator in a mobile telecommunication receiver or transmitter.
PLL-based frequency synthesizers include a 96 divider consisted of a Master-Slave high frequency prescaler and a 48 divider which uses TSPC as D type flip-flop, a no output glitch phase/frequency detector (PFD), a charge pump (CP), a second order low pass filter uses as a loop filter (LP) and a LC-tank voltage control oscillator (VCO) having a tuning range from 2.28 to 2.42 GHz. The PFD circuit detects the phase and frequency difference between the reference signal and the feedback signal, then produces the UP and DN signals. The CP and LP circuits transfer the digital signal output from PFD to an analog signal Vc to control the output frequency of VCO. The divider employs a master-slave circuit, asynchronous and synchronous circuits to provide a 96 divider.
All circuits are designed using 0.25 um TSMC 1P5M CMOS model. The power consumption is 52.3 mW. The total chip area is 1701 × 1365 μm2.

目 錄
中文摘要 Ι
英文摘要 Ⅱ
圖目錄 Ⅴ
表目錄 Ⅷ
第 一 章 緒 論 1
1-1 動 機 1
1-2 利用鎖相迴路技術設計的頻率合成器 ……………… 2
1-3 論文組織 ……………………………………………… 3
第 二 章 鎖相迴路理論基礎與架構 4
2-1簡介 …………………………………………………… 4
2-2 相頻偵測器 …………………………………………… 5
2-3 電荷幫浦 ……………………………………………… 8
2-4 迴路濾波器 …………………………………………… 10
2-5 電荷幫浦式鎖相迴路設計 …………………………… 12
2-5-1 二階鎖相迴路 ………………………………… 12
2-5-2 三階鎖相迴路 …………………………………… 13
2-6 除頻器電路設計 ……………………………………… 17
第 三 章 壓控震盪器(VCO)電路設計 19
3-1 壓控震盪器簡介 ……………………………………… 19
3-2 LC-tank VCO設計原理 ………………………………… 21
3-2-1 諧振電路 ……………………………………… 22
3-2-2 主動元件設計 ………………………………… 23
3-3 低功率設計 …………………………………………… 25
3-4 變容器 ………………………………………………… 26
3-5 電感模型………………………………………………… 29
第 四 章 頻率合成器之設 31
4-1 相位/頻率偵測器之設計 ……………………………… 31
4-1-1 死角（dead zone）的探討 …………………… 31
4-1-2 相位/頻率偵測器設計 ………………………… 32
4-2 電荷幫浦與迴路濾波器之設計 ……………………… 36
4-3 壓控震盪器設計 ……………………………………… 39
4-4 除頻器設計 …………………………………………… 42
4-5 鎖相迴路的參數及定義 ……………………………… 47
4-6 模擬結果與電路佈局 ………………………………… 49
第 五 章 結 論 與 建 議 57
5-1 結論 ………………………………………………… 57
5-2 建議未來研究方向……………………………………… 58
參 考 文 獻 59

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