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研究生:吳彥緯
研究生(外文):Yen Wei Wu
論文名稱:低電源用異質接面雙極性電晶體之製造
論文名稱(外文):Fabration of Low Power Supply Heterojunction Bipolar Transistor
指導教授:羅文雄羅文雄引用關係
指導教授(外文):Wen Shiung Lour
學位類別:碩士
校院名稱:國立海洋大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:51
中文關鍵詞:低電源用數位階梯式超晶格型的射極結構多重超晶格異質接面雙極性電晶體濕式氧化表面處理砷化鋁鎵/砷化鎵
外文關鍵詞:Low Power SupplyDigital Graded Superlattice-EmitterMultiple Quantum WellHBTwet-oxidized surface treatmentAlGaAs/GaAs
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在本論文中,為求有效降低因異質界面結合所造成導電帶上的位能尖,我們提出一種運用量子井所形成數位階梯式超晶格型的射極結構。經由理論及實驗數據的分析,我們得到相當不錯的驗證。在理論方面:藉由轉移矩陣方法可知,經使用數位階梯式超晶格型的射極結構,射極、集極間的穿隧電子流的確已增加因而有效的平滑掉導電帶上的位能尖。而實驗方面:我們也成功的製造出含與不含磷化銦鎵/砷化鎵保護層的數位階梯式超晶格型的射極結構異質接面電晶體,並且特性如我們所預期。
為了做比較,我們拿一般型含磷化銦鎵保護層的磷化銦鎵/砷化鎵異質接面電晶體與本論文所提出的結構相比(兩結構的摻雜濃度、各層厚度皆相同)。經分析實驗數據後得知,在集極電流等於1微安培時,起始電壓各為0.87伏特(本文提出的結構)及0.95伏特(比較的結構),而補償電壓各為55毫伏特(本文提出的結構)及110毫伏特(比較的結構)。由上可知,使用此結構的確可有效地平滑掉導電帶上的位能尖且電流增益為250。此外,當我們再使用磷化銦鎵/砷化鎵保護層於本文所提出的結構上時,電流增益更可高至385,由以上各優點可知,此元件非常適合應用於低功率消耗電路。
另外,我們也進行濕氧化表面處理之研究。雖然在處理的初期特性變差,但再經過一段的氧化處理之後,特性會隨較穩定性氧化層的慢慢形成而變佳,因此經實驗數據分析得知,當含鋁量高的砷化鋁鎵/砷化鎵層曝露在空氣中時,將會受到環境影響而有所變化,而適當的表面處理技術將會是將來可靠性分析的一大課題。

In this thesis, we report a newly designed Al0.45Ga0.55As/GaAs digital graded superlattice emitter (DGSE) structure, which forms a step-wise graded composition to smooth out the potential spike as it is combined with a p-base layer first. Both theoretical derivation and experimental results of DGSE bipolar transistor are included. We obtained good agreements between theoretical calculation and experimental data. Theoretical calculation shows that tunneling current of electron has effectively increased with using DGSE structure. Experimentally, we have successfully fabricated DGSE bipolar transistor with and without InGaP/DGSE passivation layer.
For comparison with InGaP/GaAs ones with an InGaP passivation layer, the VON(E-B) (the collector current exceeds 1 μA) of InGaP/DGSE HBT is 0.87 V, which is 80 mV lower than the 0.95-V VON(E-B) of an InGaP HBT over a wide rang of current level. And the collector ideality factor hc are 1.2 and 1.1 as well as the base ideality factor hb are 1.9 and 1.1 respectively. On the other hand, the small offset voltage of 55 mV as compared to a 110-mV offset voltage of our compared device reveals that the DGSE structure really eliminates the spike resulting from DEC.The current gain of the studied HBT is as high as 250 and is even enhanced to 385 with an InGaP passivation layer.
Second, we proposed a method of wet-oxidation treatment in this study. Experimental results reveal that the studied HBT’s exhibit reduced collector currents at a fixed base current in the early stage of wet-oxidation treatment. However, better surface passivation and higher current gain are available after an appropriate wet-oxidation treatment is used to reduce base current. Therefore, we still obtained high current gain, small offset voltage, low knee voltage, low turn-on voltage, and breakdown voltage by an appropriate wet-oxidation treatment.

Abstract 2
Table and Figure Captions 4
Chapter 1 Introduction 6
Chapter 2 Turn-On Voltage Reduction in Al0.45Ga0.55As/GaAs Digital Graded Superlattice-Emitter (DGSE) Bipolar Transistors 8
2 — 1 Introduction 8
2 — 2 Theoretical Analysis of the Multiple Quantum Well 10
2 — 3 Material Structures and Device Fabrication 18
2 — 3 — 1 The Material Structures of Device 18
2 — 3 — 2 Device Fabrication 19
2 — 4 Experimental Results and Discussion 26
Chapter 3 Al0.45Ga0.55As/GaAs DGSE HBT performance improvement
by wet-oxidized graded-like superlattice-emitter 33
3 — 1 Introduction 33
3 — 2 Experimental Results and Discussion 34
3 — 2 — 1 Experiments 34
3 — 2 — 2 Results and Discussion 36
Chapter 4 Conclusions and Expectations 45
References 47

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