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研究生:蔡文結
研究生(外文):Wen-Chieh Tsai
論文名稱:2.4GHzCMOS射頻接收器之前級電路設計
論文名稱(外文):The Design of A 2.4GHz CMOS RF Receiver Front-End
指導教授:劉萬榮
指導教授(外文):Wan-Rone Liou
學位類別:碩士
校院名稱:國立海洋大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:98
中文關鍵詞:射頻接收器
外文關鍵詞:RF receiver front end
相關次數:
  • 被引用被引用:5
  • 點閱點閱:258
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本論文描述了一個2.4GHz CMOS射頻接收器之前級電路的設計。這個接收器包含一個低雜訊放大器、一個降頻混波器與一個壓控震盪器。首先,我們分別完成了加入級與級之間之匹配電感的低雜訊放大器與單端混波器。台積電CMOS 0.25um製程的低雜訊放大器,可以達到S11為-20dB、增益為10dB與雜訊為5dB的量測結果;然而台積電CMOS 0.35um製程的混波器,則其轉換損失、1dB壓縮點與第三階交會點的量測結果為3.5dB、-12dBm與0dBm。此外,為了能夠實現全積體化的射頻接收器前端,我們採用台積電CMOS 0.35um製程,把有帶通濾波器的低雜訊放大器、單端輸入-雙平衡混波器與壓控震盪器整合在一個晶片上。最後,射頻接收器前端的模擬特性為19dB的增益、5.6dB的雜訊、-16dBm的第三階交會點與62mW的功率損耗。

This thesis presents the design of a 2.4GHz CMOS RF receiver front end. The receiver contains a low noise amplifier (LNA), a down conversion mixer and a voltage control oscillator (VCO). Firstly, we implement the LNA with an inter-stage matching inductor and a single ended mixer, respectively. The LNA used TSMC 0.25um CMOS process features the measured results of —20dB S11, 10-dB gain and 5-dB noise figure, while the mixer used TSMC 0.35um CMOS process exhibits the measured results of 3.5-dB conversion loss, -12-dBm 1dB-compression point and 0-dBm IIP3. Furthermore, in order to realize a fully integrated receiver front end, we integrate the LNA with a bandpass filter, the single ended input-double balance mixer, and the VCO into a single chip in TSMC 0.35um CMOS process. Finally, the RF receiver front-end shows the simulation results of 19-dB conversion gain, 5.6-dB noise figure, -16-dBm IIP3 and 62mW power dissipation.

致謝…………………………………………………………………………Ⅰ
中文摘要……………………………………………………………………Ⅱ
英文摘要……………………………………………………………………Ⅲ
圖目錄………………………………………………………………………Ⅵ
表目錄………………………………………………………………………Ⅹ
第一章 緒論………………………………………………………………1
1-1 動機………………………………………………………………1
1-2 論文綱要…………………………………………………………2
第二章 射頻接收器前端…………………………………………………3
2-1 接收器簡介………………………………………………………3
2-2 外差接收器所遇到的問題………………………………………6
2-3 外差接收器的特性參數…………………………………………10
第三章 低雜訊放大器設計………………………………………………15
3-1 簡介………………………………………………………………15
3-2 輸入阻抗匹配……………………………………………………16
3-3 雜訊分析…………………………………………………………18
3-4 設計流程…………………………………………………………25
3-5 模擬結果…………………………………………………………31
3-6 帶通放大器設計…………………………………………………36
第四章 混波器與壓控振盪器設計………………………………………46
4-1 混波器……………………………………………………………46
4-2 壓控振盪器………………………………………………………60
第五章 射頻接收器前端的實現…………………………………………69
5-1 積體化的螺旋形電感……………………………………………69
5-2 佈局考量…………………………………………………………71
5-3 低雜訊放大器的實現……………………………………………72
5-4 單端混波器的實現………………………………………………75
5-5 射頻接收器前端的實現…………………………………………80
第六章 結論………………………………………………………………85
參考文獻 ……………………………………………………………………86

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