臺灣博碩士論文加值系統

本論文設計一個高解析度的超取樣delta-sigma類比數位轉換器。整個類比數位轉換器包括類比調變器與數位降頻濾波器兩個部份。類比調變器採用超取樣128倍與MASH(多級雜訊整型)四階架構來達到頻寬20kHz解析度14bit的效能。另外，在調變器電路實現方面，我們使用了全差動交換電容式技術去完成。除了調變器之外，在本論文中也設計並實作一個低功率、省面積、以及可規劃的數位降頻濾波器。本降頻濾波器架構主要由降頻32倍之5階sinc濾波器及兩個降兩倍之halfband濾波器所組合而成。為減少sinc濾波器在頻寬內之衰減，本論文亦使用一補償濾波器以避免增益不一的情況。在調變器的系統中其取樣率為6.144MHz，使用±2.5V電源供應，總功率消耗為62mW。佈局面積為990um x 900um，並且使用聯華積體電路製造公司(UMC)的0.5um 2P2M製程來製作。在數位降頻濾波器方面則使用美商智霖公司(Xilinx) Virtex系列晶片的現場可規劃邏輯陣列(FPGA)來實現。

A high-resolution fourth-order cascade ΔΣ analog-to-digital modulator is proposed in this paper. The entire analog-to-digital converter contains two section: an analog modulator and a digital decimation filter. This modulator with oversample rate of 128 achieves a resolution of 14-bit and signal bandwidth is 20KHz. The 4th order MASH (multi-stage noise shaping) used in this design. In circuit implement stage, we use the technology of fully differential switched-capacitor to accomplish the modulator. Along with the modulator, a low-power, area-efficient, and programmable digital decimation filter is also design and implementated in this paper. The decimation filter architecture consists of a fifth-order sinc filter by decimation by 32x and two halfband filters followed by decimation by 2x. For a sinc filter, a compensation filter can be used to flatten the passband frequency response. The system sample rate is 6.144MHz, the power supply and the power consumption of the modulator is ±2.5V and 62 mW, respectively. The fabrication technology is UMC 0.5um 2P2M technology for analog modulator, and the layout area is 990um * 900um. We implement the decimation filter into Xilinx’s Virtex FPGA XCV400EPQ240 for digital filter.

中文摘要
英文摘要
圖表目錄
目錄
第一章 緒論 1
1.1 研究動機………………………………………………………1
1.2 類比數位轉換器的簡介………………………………………1
1.3 Sigma-Delta類比數位轉換器的優點 ………………………2
1.4 應用場合………………………………………………………3
1.5 論文章節編排…………………………………………………3
第二章 超取樣 調變器之系統架構與原理………………………4
2.1 簡介……………………………………………………………4
2.1.1 脈波調變之類比數位轉換方式 ……………………………4
2.1.2 奈奎氏取樣（Nyquist Rate）定理 ………………………5
2.1.3 量化（Quantization）及性能分析 ………………………6
2.2 超取樣脈波調變的轉換方式 …………………………………8
2.2.1 超取樣定理說明與系統描述 ………………………………8
2.2.2性能分析 ……………………………………………………9
2.3 雜訊整形與和差調變器（ Modulator） …………………10
2.3.1 和差調變器的線性模型 ……………………………………11
2.3.2 一階和差調變器 ……………………………………………12
2.3.3 二階和差調變器 ……………………………………………14
2.3.4 高階和差調變器與MASH架構的優缺點 ……………………17
第三章 MASH 2-2(四階)和差調變器 ……………………………19
3.1 MASH2-2架構探討………………………………………………19
3.1.1 數位抵消網路之轉移函數 …………………………………20
3.2 和差調變器的非理想性因素分析…………………………24
3.2.1 類比與數位部份內的增益不匹配…………………………24
3.2.2 有限的運算放大器直流增益 ……………………………25
3.2.3 安定時間與轉換率的限制 ………………………………26
3.3 Signal Scaling ……………………………………………27
3.4 調變器之主要電路設計與考量 ………………………………31
3.4.1 類比開關/傳輸閘 …………………………………………32
3.4.2 非重疊時產生器（Non-overlap Clock Driver）………33
3.4.3 電容 ………………………………………………………36
3.4.4 全差動運算放大器（Fully differential OP-Amps）…36
3.4.5 比較器（Comparator）/ 1-bit A/D ……………………40
3.4.6 1-bit數位類比轉換器(1-bit D/A) ……………………43
3.4.7 數位消除邏輯（Digital Cancellation Logic，DCL） 44
3.5 MASH2-2調變器硬體電路實現 ………………………………51
3.5.1 交換電容電路的設計原理 ………………………………51
3.5.2 整體MASH2-2調變器電路 …………………………………53
第四章 降頻濾波器(Decimation filter) ………………………56
4.1 降頻濾波器系統架構 ………………………………………56
4.2 Sinc-濾波器 …………………………………………………59
4.3 數位濾波器……………………………………………………62
4.3.1 特性介紹 ……………………………………………………62
4.3.2 降頻因子順序及最佳化級數之決定 ………………………65
4.3.3 低通濾波器的規格 …………………………………………66
4.3.4 最佳化設計演算法與Halfband filter特性 ……………67
4.4 數位濾波器的設計與模擬 …………………………………68
4.4.1 係數(Coefficient) ………………………………………68
4.4.2 CSD碼(Cannonic Signed Digits Code) …………………71
4.5 數位濾波器硬體實現架構 …………………………………72
4.5.1 線性相位架構 ………………………………………………72
4.5.2 巢狀式乘法(Nested Multiplication) …………………73
4.5.3 實現架構的取捨 ……………………………………………74
4.5.4 算術單元 ……………………………………………………76
4.5.5 隨機存取記憶體(Ram)的配置與多降頻率定址法 ………77
4.5.6 唯讀記憶體(ROM)的配置……………………………………79
4.6 估測整體 ADC性能……………………………………………80
4.7 使用Xilinx FPGA實作數位濾波器 …………………………82
4.7.1 在Xilinx上降頻濾波器的模擬 …………………………83
第五章 電路實體佈局………………………………………………86
5.1 簡介 …………………………………………………………86
5.2 調變器電路之佈局(Layout)考量 …………………………86
5.3 整個調變器佈局圖 …………………………………………88
5.4 降頻濾波器的FPGA佈局圖 …………………………………89
5.5 量測方法 ……………………………………………………90
第六章 結論與未來研究方向 ……………………………………92
6.1 結論 …………………………………………………………92
6.2 未來發展方向 ………………………………………………92
參考文獻 ……………………………………………………………93

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