隨著通訊技術的日新月異,通訊系統的設計也有著快速的發展.為了兼顧軟體實現的彈性及硬體實現的計算效能,我們提出一個可規格化的通訊處理器.此通訊處理器提供四種工作模式,包括802.11a正交分頻多工(OFDM)接收機,802.11b直接序列展頻(DSSS)接收機,數位音訊廣播(DAB)接收機,以及數位視訊廣播(DVB)接收機.
在本篇論文中,我們分析了這四種模式的運作及計算複雜度,並將其中較複雜的運算功能分類並以硬體實現,利用重複使用的方式可以降低整體的複雜度及面積大小.因此,我們所提出的通訊處理器包含了四大運算區塊,其中快速複立葉轉換(FFT)方塊,維特比(Viterbi)解碼方塊及關聯(Correlation)運算方塊是由硬體實現,而較小量的運算則交由軟體或是可程式化的硬體來處理.
此外,我們會描述並解釋正交分頻接收機及直接序列展頻接收機的設計,以及浮點運算和定點運算的模擬.經由定點運算的模擬的結果,整個通訊處理器的架構便可依此建立.

In this thesis, the design of a scalable communication processor
is presented. Four modes are defined in the processor to provide
the scalability, including 802.11a OFDM receiver, 802.11b
DSSS/PBCC receiver, DAB receiver and DVB receiver. The functions
and computation complexity in the four modes will be analyzed to
group into three hardware blocks. The categorization of the
operations reduces the whole hardware complexity by reusing the
hardware blocks.
The OFDM receiver design and the DSSS/PBCC receiver design are
both proposed in this thesis. In addition, the functional and
fixed-point simulation are performed to verify the proposed
architecture. The proposed communication processor retains both
the flexibility in software design and the computation capability
in hardware.

1 Introduction
1.1 Spread Spectrum Techniques
1.2 OFDM Techniques
1.3 Implementation Issue
1.4 Organization
2 Physical Layers in 802.11a and 11b Standard
2.1 Physical Layer Specifications in IEEE 802.11a Standard
2.1.1 Rate-Dependent Parameters
2.1.2 Timing-Related Parameters
2.1.3 Preamble Structure
2.1.4 OFDM Training Structure
2.1.5 Data Scrambler and Descrambler
2.1.6 Convolutional Encoder
2.1.7 Data Interleaving
2.1.8 Subcarrier Modulation Mapping
2.1.9 Pilot Subcarriers and OFDM Modulation
2.1.10 Channelization
2.1.11 Channel Model
2.2 Physical Layer Specifications in IEEE 802.11b Standard
2.2.1 Long PLCP PPDU Format and Field Definitions
2.2.2 PLCP/High Rate PHY Data Scrambler and Descrambler
2.2.3 DSSS/PBCC Data Modulation and Modulation Rate
3 802.11a OFDM Receiver Design
3.1 Preamble Phase
3.1.1 Frequency and Frame Synchronization
3.1.2 Channel Estimation
3.2 Payload Phase
3.2.1 Symbol Timing Synchronization
3.2.2 Synchronization Error Correction Block
3.2.3 Soft Demodulation Block
3.2.4 Viterbi Decoding Block
3.3 Simulation Result
3.3.1 Simulation Parameters
3.3.2 Simulation Result
4 DSSS/PBCC Receiver Design
4.1 Synchronization
4.2 Channel Estimation
4.3 Channel Matched Filter
4.4 Decision Feedback Equalizer
4.5 Simulation Result
4.5.1 Simulation Parameters
4.5.2 Simulation Result
5 Scalable Communication Processor Design
5.1 Basic Communication Processor Design
5.1.1 Computation Power Analysis
5.1.2 Viterbi Decoder Block Design
5.1.3 FFT Block Design
5.1.4 Basic Communication Processor Architecture
5.2 Extension for DAB and DVB System
5.3 Extension for 802.11b Direct Sequence Spread Spectrum System
5.4 Fixed-Point System Simulation
5.4.1 802.11a OFDM Fixed-Point Simulation
5.4.2 802.11b DSSS/PBCC Fixed-Point Simulation
5.5 Proposed Scalable Communication Processor
6 Conclusion

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