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研究生:郭耀鴻
研究生(外文):Yao-Hung Kuo
論文名稱:應用於1.25Gbps乙太網路收發器的時脈與資料復原電路之研究和設計
論文名稱(外文):Research and Design on Clock and Data Recovery for 1.25Gbps Gigabit Ethernet Transceiver
指導教授:曹 恆 偉
指導教授(外文):Hen-Wai Tsao
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:89
中文關鍵詞:時脈與資料復原電路乙太網路收發器
外文關鍵詞:Clock and Data RecoveryGigabit Ethernet Transceiver
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1.25Gbps乙太網路收發器是由將10位元平行資料串列化的發射器和將接收資料去串列化的接收器所組成。時脈與資料復原電路在接收器中是一關鍵單元,它能決定每個資料位元的邊界,對齊10B的訊框,追隨頻率差所造成逐漸相位的漂移。
在本論文中,將介紹幾種時脈與資料復原電路的架構。為了正確還原所接收的數位資料將採用TSMC 0.35um製程實現一個數位迴授控制的系統。此一採用3倍超取樣技術的超取樣資料復原電路能在有些微頻率差的系統中正確復原所傳送的資料。
在第四章中,將談論一個VCO操作於半速率的時脈與資料復原電路。為了克服頻率獲取的問題,此CDR除了相位偵測器,還納入一頻率捕捉的機制。頻率比較器只有在VCO振盪頻率已經很接近工作頻率時才會將迴路切換到資料相位追蹤的模式,晶片仍然以TSMC 0.35um製程實現。模擬結果顯示它能將1.25Gbps的資料復原。

The transceiver is composed of a transmitter that serializes 10-bit parallel data and a receiver that deserializes serial data back into 10-bit parallel data. A clock and data recovery(CDR) circuit is one of the key components of optical receiver , which must determine the edges of each data bit ,align the bits into the proper frame boundaries as complete words , and follow gradual phase shift caused by frequency differences.
In this thesis, several clock and data recovery architectures will be introduced.
To recover the received signal to digital binary data correctly, a system with a digital feedback control loop will be implemented with a 0.35um CMOS technology .With 3X-oversampling technique,the signal transmitted in a plesiochronous system could be recovered correctly by the oversampling data recovery system with the data rate at 1.25Gbps.
In Chapter 4, A Clock/Data Recovery (CDR) PLL with a VCO running at half the rate for gigabit serial data communication is described. In order to remedy the acquisition problem, CDR incorporate frequency detection in addition to phase detection. The frequency comparator activiates a phase tracking operation only the frequency lock is obtained when the external reference and VCO frequencies are within 200ppm. The CDR was designed using TSMC 0.35um process parameters. Simulation results show that the circuit is capable of recovering clock and data at a speed of 1.25Gbps.

第一章 介紹
1.1動機 ………………………………………………………………….1
1.2 1000BASE-X實體層簡介…………………………………………….1
1.3 系統規格簡介 ………………………………………………………4
1.4論文組織……………………………………………………………..4
第二章 時脈與資料復原電路的基礎
2.1抖動的定義…………………………………………………………..6
2.2時脈與資料復原電路的功能………………………………………..8
2.3時脈與資料復原電路的架構………………………………………..10
2.3.1傳統鎖相迴路方式的CDR……………………………………11
2.3.2相位選擇式的CDR…………………………………………. 15
2.3.3追蹤式相位復原電路………………………………………..16
2.3.4 超取樣資料復原電路……………………………………….17
2.4 相位偵測器的分類
2.4.1線性相位偵測器……………………………………………..18
2.4.2非線性相位偵測器…………………………………………..18
2.4.3平行處理的追蹤式相位復原電路所採用的相位偵測器之比較
2.4.3.1 二倍超取樣相位偵測器……………………………….20
2.4.3.2三倍超取樣相位偵測器………………………………..21
第三章 乙太網路收發器
3.1接收器(Receiver)…………………………………………………..27
3.2延遲鎖定迴路(DLL)的設計………………………………………….28
3.2.1穩定度分析…………………………………………………..28
3.2.2 PLL 與 DLL的比較………………………………………….31
3.2.3相位偵測器…………………………………………………..32
3.2.4 DLL啟動電路………………………………………………..32
3.2.5全差動的延遲單元…………………………………………..34
3.2.6複製迴授電流源偏壓電路……………………………………36
3.2.7充電泵電路…………………………………………………..37
3.2.8 延遲鎖定迴路閉迴路模擬…………………………………..38
3.3 數位式鎖相迴路的演算法和實現…………………………………..39
3.3.1時脈的復原…………………………………………………………39
3.3.2資料的復原………………………………………………………..41
3.3.3資料旋轉器……………………………………………………43
3.3.4同步器………………………………………………………..45
3.3.5資料選擇器……………………………………………………46
3.3.6 DPLL的相位偵測過程……………………………………….46
3.3.7相位指標器……………………………………………………48
3.3.8 DPLL整體模擬的邏輯時序圖……………………………….50
3.3.9資料取樣器…………………………………………………..52
3.4晶片佈局……………………………………………………………….53
第四章 半速率時序與資料復原電路
4.1 架構簡介……………………………………………………………..55
4.2電路設計……………………………………………………………….57
4.2.1鎖相迴路……………………………………………………….57
4.2.1.1鎖相迴路(PLL)的線性模型…………………………..57
4.2.1.2 相頻偵測器/相位偵測器……………………………..62
4.2.1.3充電泵………………………………………………….63
4.2.1.4壓控振盪器/壓控延遲線……………………………..64
4.2.2具磁滯能力的頻率比較器…………………………………….66
4.2.3接收器的前端電路…………………………………………….70
4.2.4半速率時序與資料復原電路系統的整合模擬……………….72
4.3 佈局平面圖…………………………………………………………….74
4.4預計規格列表………………………………………………………….75
4.5 測試考量……………………………………………………………….75
第五章晶片量測結果
5.1乙太網路接收器………………………………………………………78
5.1.1延遲鎖定迴路的量測環境…………………………………….78
5.1.2超取樣復原電路的量測環境………………………………….79
5.1.3 位元誤碼率(BER)的量測環境……………………………….82
5.2半速率時序與資料復原電路………………………………………. ..82
5.2.1頻率比較器的量測…………………………………………..82
5.2.2時脈與資料復原電路的量測………………………………..83
第六章 結論

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