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研究生:張祐齊
研究生(外文):Yu-Chi Chang
論文名稱:行動通訊接收機中數位式I/Q不平衡與位準飄移補償之研究
論文名稱(外文):Digital I/Q Imbalance and DC Offset Compensation for Mobile Receivers
指導教授:闕志達
指導教授(外文):Tzi-Dar Chiueh
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:105
中文關鍵詞:I/Q不平衡位準飄移
外文關鍵詞:I/Q imbalanceDC offset
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在這一篇論文中介紹了各種數位補償的方法分別來解決在低中頻 (low-IF)架構中所發生的I/Q不平衡問題及direct-conversion架構中所發生的位準飄移的問題。在低中頻架構中是採用一個quadrature降頻器把射頻信號轉移到一個非常低的中頻做通道選擇再進一步降到基頻。然而quadrature降頻器由於是類比電路,因此它的兩個分支或多或少都會有不平衡的情形出現,這個不平衡將使得鏡像拒斥比 (image rejection ratio) 無法達到理想中的無限大,也因此接收到的信號還是會受到鏡像 (image) 的干擾。為了補償這個I/Q不平衡的情況,我們採用了相關係數估計並扣除的方法 (correlation estimation and cancellation),這個演算法相當簡單而且跟目前被廣泛提出的可適性干擾消除器 (adaptive interference canceller) 比起來,它更有穩定的特質並且能提供非常好的補償品質。在GSM的接收環境中,在做完I/Q不平衡補償之後,信號干擾比 (signal-to-interference ratio) 可以達到30dB以上。在direct-conversion的架構中所發生的主要問題是位準飄移。由於在電路中各個元件的輸入端之間的隔絕並無法做到百分之百,因此在做降頻動作時會因為自我相乘 (self-mixing),使得接收到的信號的位準會被偏移一個值。為了消除這個偏移的位準,我們提出了一個雙迴圈架構輔以兩階段式動態位準偏移補償演算法,使得在GSM的接收環境中,要達到10^(-6)的位元錯誤率,只需要比理想電路所需的信號雜訊干擾比 (SINR) 大2dB即可。

Recent research has been focused on the development of monolithic receiver architectures, especially using low-cost CMOS technology. Among different receiver architectures, low-IF and direct-conversion architectures are two potential candidates for monolithic integration. However, they suffer from their own problems. In low-IF architecture, quadrature down-conversion is used to transfer RF signals to a very low IF frequency and unavoidable imbalances between the I- and Q-branches result in finite and usually insufficient rejection of the image signals which causes interference. We carry out the signal analysis of an imbalance low-IF receiver and use a simple digital algorithm, correlation estimation and cancellation, to compensate I/Q mismatch. In the GSM environment, the resulting SIR is above 30dB after compensation. Another architecture suitable for monolithic integration is the direct-conversion architecture and it suffers
from a DC offset problem resulting from self-mixing. The DC ffset will overwhelm the desired signal in baseband and thus leads to serious errors. We propose a dual-loop architecture with a two-step algorithm to remove the DC offset. After compensation, there is only about 2dB degradation at BER is
10^(-6) in GSM receivers.

第一章 簡介 (Introduction)
第二章 傳統與新穎的接收機架構 (Classical and Modern Receiver Architectures)
第三章 收發機及通訊通道模型 (Transceiver and Channel Model)
第四章 在低中頻架構中I/Q不平衡補償 (I/Q Imbalance Compensation in Low-IF Receivers)
第五章 在Direct-Conversion架構中的位準飄移補償 (DC Offset Cancellation in Direct-Conversion Receivers)
第六章 總結 (Conclusion)

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