摘要
隨著網際網路的的發展，無線區域網路(wireless local-area network)漸漸地成了網路行動通訊的解決方案，使我們無論在何時何地都可獲得我們想要的資訊。
本文重點是放在IEEE 802.11b無線區域網路(WLAN)的前端接收器的設計和實作，包含低雜訊放大器(low-noise amplifier)、射頻混波器(RF down-conversion mixer) 、和多相位濾波器(polyphase filter)，均採用台灣積體電路公司的0.25um的CMOS製程。我們的接收器使用超外差 (super-heterodyne)的架構，射頻(RF)的頻率是在2.4G赫茲，中頻(IF)的頻率是在374M赫茲。
以ADS軟體模擬，低雜訊放大器在高增益模式(high-gain mode)下，有19dB 的功率增益(power gain)，1.76dB 的雜訊指數(noise figure) ，-19dBm 的輸入三階交叉點(IIP3)，12mA 的電流消耗，在低增益模式下有-12dB功率增益，8.85dB 的雜訊指數，3dBm輸入三階交叉點，8mA的電流消耗。混波器在-7dBm大小的本地震盪(LO)下，有6.8dB的能量增益，19dB的雜訊指數，4.9dBm 輸入三階交叉點，and 7.5mA的電流。多相位濾波器有40dB的鏡像(image)濾波。
第一章 簡介
隨著科技的進步，近幾年無線區域網路慢慢興起，低電壓，低功率消耗，以及朝向CMOS製程整合是近幾年來無線通訊前端(RF front-end)電路的主流研究方向。本章概略地了介紹了整個接收器各個電路的功能。
論文的第二章討論了不同接收器架構的功能以及設計時的考量，同時也簡介設計低功率放大器、混波器、和多相位濾波器設計時的重要參數。
第三章討論所設計之低功率放大器、混波器、及多相位濾波器所採用的架構，以及使用ADS軟體模擬之結果。
第四章敘述簡單的低功率放大器的測試版晶片量測結果，以及整個接收器晶片之實作、佈局上的考量。
第五章總結本篇論文並給予未來研究工作上的建議。
第二章 接收器架構
我們總共討論了超外插(super-heterodyne)、低中頻(low-IF)、直接轉換(direct conversion)三種不同的接收器的架構，並且就實作的難易程度、整合度、省電程度等等來比較他們之間的優缺點，說明為何我們要採用超外插架構，它最大的好處在於它提供了較高的訊號選擇性(selectivity)以及靈敏度(sensitivity)。在超外插式接收機中，常常遇到的的問題在於鏡像(image)的消除以及中頻的設定。
在設計低雜訊放大器和混波器時，有一些重要的設計參數要考量：轉換增益(conversion gain)、雜訊指數(noise figure)衡量電路所產生的雜訊、輸入三階交叉點(IIP3)以及輸入-1dB功率飽和點(input P-1dB)衡量線性度。輸入阻抗匹配、電壓以及功率消耗也是設計的重點。而設計多相位濾波器需要由增益和頻寬來考量要串聯多少級，串愈多級對鏡像的濾波(rejection)愈強但訊號的損失(loss)愈大，此外對於電阻和電容值的變異(variation)還有不對稱性(mismatch)也是需要注意的地方。
第三章 2.4GHz CMOS接收器的設計
基於線性度和靈敏度的考量，我們提出了有兩種增益模式的低雜訊放大器，高增益模式來實現高靈敏度，低增益模式來實現高線性度。我們是朝低雜訊、維持輸入阻抗匹配、省電等等方向來設計的。
由於吉爾伯特(Gilbert)的混波器對本地震盪(LO)有很好的隔絕度(isolation)，所以我們的混波器也是採用這種架構。但是這種混波器是雙端輸入的，而我們的低雜訊放大器是單端輸出的，故我們用共閘─共源(common gate-common source)作為混波器的輸入介面來解決問題，而同時又能維持良好的特性。
多相位濾波器由於要提供至少25dB的鏡像濾波，再加上考慮到電阻和電容值25%的變異，故我們決定串接兩級濾波器來達到我們的要求，軟體模擬有45dB的濾波效果，故還有20dB的餘裕(margin)保留給不對稱性(mismatch)所造成的影響。
整個前端接收器在高增益模式下有32dB的電壓增益、3dB的雜訊指數、以及-23dBm的輸入3階交叉點，共用了29mA的電流。在低增益模式下有2dB的電壓增益、30dB的雜訊指數、以及2dBm的輸入3階交叉點，共用了25mA的電流。
第四章 晶片實作與量測結果
首先介紹了一個曾經實作過的低雜訊放大器的簡單測試版本，量測結果發現遇到了震盪的問題，歸究其原因是佈局(layout)發生了問題，大量的輸出訊號經由基體(substrate) 耦合的雜訊影響了偏壓(bias)電路，造成了穩定性的問題。而這個寶貴的經驗可以讓我們在前端接收器的實作上加以注意並改善。
低雜訊放大器的佈局是非常需要注意的，因為這會影響到雜訊指數和穩定度，尤其要考慮到基體的雜訊耦合效應。混波器和多相位濾波器最重要的是對稱性(symmetry)的問題，因為本地震盪和鏡像的消除非常仰賴信號路徑的匹配(matching)。而為了提高多相位濾波器本身的對稱性，我們重新安排了多相位濾波器的佈局。
第五章 結論與未來工作
在本篇論文中，我們提出了CMOS 0.25um製程的2.4GHz無線區域網路的前端接收機，其中低雜訊放大器有相差30dB增益的兩種增益模式，在兩種模式下阻抗匹配幾乎是相同的。我們用共閘─共源的混波器解決低雜訊放大器單端輸出轉混波器雙端輸入的介面問題，並且維持原本吉爾伯特(Gilbert)混波器架構下應有的性能。多相位濾波器提供了能在晶片上作鏡像濾波的解決方案。總合來說，我們提出了一個可接收大範圍訊號強度、對鏡像濾波佳、高靈敏度(sensitivity)的前端接收器。
至於未來的工作，除了要利用不同的佈局來驗證低雜訊放大器穩定度的問題，而我們提出的混波器的雜訊指數只是堪用而已，其實還有可以改進的空間。

ABSTRACT
With the growth of Internet, we can always on-line get information and knowledge. Wireless local-area network (WLAN) is a new idea for mobile communication that allows us to connect to the Internet anywhere without wire.
Our research concentrated on the analog design of a 802.11b WLAN transceiver front-end. The 802.11b front-end in this work is divided into 5 parts: Front-End Receiver, Voltage Control Oscillator (VCO), Phase Lock Loop (PLL), Front-End Transmitter and Intermediate Frequency (IF) circuits. This Thesis emphasizes on the CMOS front-end receiver design and its implementation. The front-end receiver circuit includes a dual-gain mode low-noise amplifier (LNA), two modified Gilbert cell Mixers, and a polyphase image-rejection filter. Our target is to integrate these five parts into a single chip integrated circuit (IC). Besides, Electro-Static-Discharge (ESD) protection circuit, package model and transmission line effect on printed-circuit board (PCB) have also been considered.
We use TSMC 0.25um CMOS process technology. The transceiver design is based on super-heterodyne double down-conversion structure, where RF signal locates at 2.4GHz, IF signal locates at 374MHz and LO signal locates at 2GHz. Power supply is 2.7V.
If the proposed LNA is set at high gain mode, it has 19dB power gain, 1.76dB noise figure, -19dBm IIP3, and 12mA current consumption. At low gain mode the LNA has -12dB power gain, 8.85dB noise figure, 3dBm IIP3, and 8mA current consumption. As for the down-conversion mixer, it has 6.8dB power gain, 19dB noise figure, 4.9dBm IIP3, and 7.5mA current consumption. The polyphase filter provides 40dB image rejection in the receiver chain.

TABLE OF CONTENTS
ABSTRACT
TABLE OF CONTENT i
LIST OF FIGURES v
LIST FO TABLES viii
CHAPTER 1. INTRODUCTION 1
1.1 Background and Motivation……………………………………………1
1.2 Thesis Outline …………………………………………………………2
CHAPTER 2. REVIEW OF RECEIVER ARCHITECHTURES 5
2.1 Receiver Architecture…………………………………………………5
2.1.1 Super-Heterodyne Architecture……………………………………5
2.1.2 Low-IF Architecture…………………………………………………7
2.1.3 Zero-IF Architecture ………………………………………………8
2.1.4 Comparison and Our Choice ………………………………………11
2.2 General Considerations in LNA ……………………………………12
2.2.1 Conversion Gain ……………………………………………………13
2.2.2 Noise Figure…………………………………………………………13
2.2.3 Gain Compression and Third-Order Intermodulation Distortion……………………………………………………………………14
2.2.4 Stability ……………………………………………………………15
2.3 General Considerations in Mixer …………………………………16
2.3.1 Conversion Gain ……………………………………………………16
2.3.2 Noise Figure…………………………………………………………17
2.3.3 Linearity ……………………………………………………………17
2.3.4 Port to Port Isolation……………………………………………18
2.4 Image and Polyphase Filter…………………………………………18
2.4.1 Complex Signal and Image Rejection……………………………19
2.4.2 Gain and Bandwidth of Polyhase Filter ………………………20
2.4.3 RC Process Variation and Mismatch ……………………………21
CHAPTER 3. DESIGN OF 2.4GHZ CMOS RECEIVER 23
3.1 Proposed 2.4 GHz CMOS LNA …………………………………………24
3.1.1 Motivation……………………………………………………………24
3.1.2 Proposed CMOS RF LNA………………………………………………27
3.1.3 Simulation Results…………………………………………………30
3.1.4 Summary of Simulation Results …………………………………35
3.2 Proposed 2.4GHz CMOS Down-Conversion Mixer……………………36
3.2.1 Motivation……………………………………………………………36
3.2.2 Proposed CMOS RF Mixer……………………………………………38
3.2.3 Simulation Results…………………………………………………40
3.2.4 Summary of Simulation Results …………………………………42
3.3 Design of Polyphase Filter…………………………………………43
3.3.1 Design Consideration………………………………………………43
3.3.2 Design Steps…………………………………………………………43
3.3.3 Simulation Results…………………………………………………46
3.3.4 Summary of Simulation Results …………………………………49
3.4 Receiver Front-End Simulation Results …………………………50
3.4.1 Models Used in Simulation ………………………………………50
3.4.2 Simulation Results of Conversion Gain and Noise Figure .52
3.4.3 Simulation Results of IIP3………………………………………53
3.4.4 Simulation Results of Image Rejection ………………………55
3.4.5 Simulation Results of Transient ………………………………55
3.4.6 Summary of Simulation Results …………………………………57
CHAPTER 4. IMPLEMENTATION AND MEASUREMENT 59
4.1 Previous LNA Testkey…………………………………………………59
4.1.1 Layout and Simulation Result of LNA Testkey ………………60
4.1.2 Measured Results……………………………………………………61
4.2 Floor Planning of Receiver…………………………………………68
4.3 Layout of Proposed LNA………………………………………………69
4.4 Layout of Proposed I/Q Mixer and Polyphase Filter …………70
4.5 Summary …………………………………………………………………72
CHAPTER 5. CONCLUSION AND FUTURE WORK 73
5.1 Conclusion………………………………………………………………73
5.2 Future Work ……………………………………………………………73
REFERENCE 75

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