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研究生:吳忠政
研究生(外文):Chung-Cheng Wu
論文名稱:二維三階上提式離散小波轉換架構
論文名稱(外文):An Architecture of 2-Dimensional 3-Level Lifting-Based Discrete Wavelet Transform
指導教授:陳順智陳順智引用關係
指導教授(外文):Shung-Chih Chen
學位類別:碩士
校院名稱:南台科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:53
中文關鍵詞:二維小波轉換上提式硬體使用率
外文關鍵詞:2-DimensionalDiscrete Wavelet Transform (DWT)Lifting-Basedhardware utilization
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離散小波轉換(DWT)是一種分析資料的方法,由於影像經過離散小波轉換後,會產生重要性不同的資料,根據這些重要性的差異,便可以針對其特性做最佳的處理,而達到更好的壓縮效果。因此,離散小波轉換相當受到重視。而離散小波轉換的應用很廣,目前已廣泛地應用在信號分析、信號壓縮、影像壓縮,以及視訊壓縮等方面。
傳統離散小波轉換是以濾波器為主,由於它所需要的計算量相當龐大,因此,新一代的小波--上提式離散小波轉換(Lifting-based DWT)在1996年被提出。由於上提式離散小波轉換擁有較傳統離散小波還低的計算複雜度,且易於實現,因此採用上提式離散小波轉換來設計,而最新的影像標準JPEG 2000 也以上提式離散小波為其主要的壓縮標準之一。
本篇論文主要是設計一個二維的上提式離散小波轉換,針對小波轉換二分之一取樣的關係,而導致其硬體使用率不高的缺點加以改良。在第一部份主要提出一個可調長度之上提式離散小波轉換架構,我們利用了二種方法來提高硬體的使用率,以降低其硬體成本,其中包括管線化的技巧以及乘法器的共用,並加入簡單的控制線路使其能夠達到多階的小波轉換。第二部份主要設計一個二維三階的離散小波轉換架構,同時處理二維三階的小波運算。我們針對列轉換以及行轉換不同的特性,分別做不同的處理,目的在於降低所需的暫存器數量,以及提高其硬體使用率。
最後以Verilog HDL 描述所提出的電路架構,再使用Synopsys的Design Compiler 進行邏輯合成。然後採用Avant! 的Apollo Layout Tools配合TSMC的0.35μm製程技術自動合成出晶片。
The discrete wavelet transform(DWT) is useful in many different fields, including signal analysis, signal compression, pattern recognition, and numerical analysis, especially in image/video compression. The DWT decomposes signals into different frequency bands, and performs a multiresolution analysis.
Because the traditional DWT is composed of filters, the VLSI implementation complexity is very high. In 1996, lifting-based DWT is proposed. The advantages of the lifting-based DWT are lower implementation complexity and less hardware resources. The lifting-based DWT is also used in the newest image standard - JPEG-2000.
In this paper, we propose two 2-D DWT architectures. In the first part, we present a salable architecture for 2-dimensional lifting-based DWT. Because of downsampling of the DWT, the hardware utilization is very low. In order to solve the problem, we propose a pipelined and merged architecture, which combines the horizontal and vertical DWT together. We also add some control circuits to make the architecture suitable for different decomposition levels. In the second part, we present an architecture for 2-D 3-level lifting-based DWT. We propose two different methods for row and column transforming to reduce the storage size of the architecture. The proposed architecture computes 2-D 3-level DWT coefficients concurrently, and achieves higher hardware utilization.
The proposed VLSI architectures are described in Verilog HDL, and synthesized by the Synopsys’ Design Compiler. Finally, the layout of the design is generated automatically by the Avant! Apollo Layout Tools in a 0.35μm 1P4M CMOS technology. The chip area is about 2055 x 2055 μm2.
摘要..............................................v
英文摘要.........................................vi
誌謝............................................vii
目次...........................................viii
表目錄............................................x
圖目錄...........................................xi
第一章 緒論......................................1
1.1 研究背景與動機...........................1
1.2 相關研究.................................2
1.3 章節概要.....................................3
第二章 離散小波轉換..............................5
2.1 前言.....................................5
2.2 小波轉換.................................6
2.3 一維離散小波轉換.........................6
2.3.1 傳統濾波器離散小波轉換..............6
2.3.2 上提式離散小波轉換..................8
2.3.3 一維三階離散小波轉換...............12
2.4 二維離散小波轉換........................13
2.4.1 二維一階離散小波轉換...............13
2.4.2 二維三階離散小波轉換...............15
2.4.3 應用於影像分解.....................16
第三章 可調長度之二維上提式離散小波轉換架構.....18
3.1 前言....................................18
3.2 上提式5/3濾波器DWT之VLSI實現............19
3.3 直接實現的方式..........................21
3.4 二維離散小波轉換之VLSI架構..............22
3.5 多階的設計..............................28
3.6 效能比較................................29
第四章 二維三階上提式離散小波轉換之硬體架構.....31
4.1 前言....................................31
4.2 基本架構................................31
4.3 二維三階離散小波轉換之VLSI架構..........32
4.3.1 列轉換的方法.......................33
4.3.2 行轉換的方法.......................33
4.3.3 硬體架構...........................36
4.4 時序分析................................42
4.5 效能與結果比較..........................44
第五章 模擬與結果...............................46
5.1 設計流程................................46
5.1 模擬結果................................47
第六章 結論.....................................50
參考文獻.........................................51
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