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研究生:邱慶觀
研究生(外文):CHING KUAN CHIU
論文名稱:深次微米元件模擬之校正技術開發
論文名稱(外文):Development of Calibration Methodology for the Simulation of Deep Submicron DRAM Devices
指導教授:張睿達
指導教授(外文):Ruey Dar Chang
學位類別:碩士
校院名稱:長庚大學
系所名稱:半導體科技研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:英文
論文頁數:68
中文關鍵詞:短通道效應反轉通道效應模擬驗證
外文關鍵詞:short channel effectreverse short channel effectsimulationcalibration
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隨著元件尺寸的縮小,會產生短通道效應(SCE),這會使的臨界電壓隨著通道的縮短而下降,因而影響元件的特性。為了要抑制SCE,大角度的離子植入(Halo implantation)是一個很常用的方法,但是這個方法會在閘集邊緣造成硼離子的聚集,因而產生反轉通道效應(RSCE)。除此之外,RSCE也會因源集和汲集的離子植入所產生的點缺陷經由隨後熱製程中的暫態快速擴散(TED)所產生。由於現今的深次微米元件中存在許多複雜的物理現象,為了要能夠利用模擬來準確的預測元件的特性,我們必須要發展出一套有效的方法來驗證模擬中的模型。
二次離子質譜儀(SIMS)分析是製程驗證的基本工作,但是SIMS只能對於一維的雜質分佈作驗證並且在介面上的定量並不是很準確。因此我們需要利用臨界電壓來做更準確的驗證。在此篇論文中,我們發展出一套驗證的方法。由於長通道元件的臨界電壓和元件的垂直結構有關,因此驗證都是由長通道元件開始。長通道元件主要是利用閘集功函數,閘集氧化層以及基底雜質分佈的臨界電壓來做驗證。我們可以利用有相同閘集材料的NMOS與PMOS並比較其臨界電壓來驗證閘集的功函數。對於氧化層以及基底的雜質分佈可使用不同的氧化層厚度以及不同的通道離子植入所產生不同的臨界電壓來做驗證。
當元件垂直方向的結構驗證完之後,我們利用短通道元件來驗證元件水平方向的雜質分佈。對於沒有口袋型離子植入(pocket-implantation or Halo-implantation) 的元件,臨界電壓的上升或下降可以利用離子植入所產生的缺陷的量以及缺陷和表面結合的速度來控制。對於有Halo-implantation的元件,我們利用臨界電壓來驗證了Halo-implantation的橫向雜質分佈。
當元件結構和雜質分佈都已經驗證完之後,可利用I-V曲線來驗證電子遷移率 (mobility).
這套驗證的方法可適用於隨機存取記憶體(DRAM)中n型與p型的周邊電路中的元件。從驗證的結果看來,模擬的值大致上都能夠準確的預測實驗的值。
Short channel effect (SCE) occurs with device shrinkage and it results in threshold voltage roll-off with the gate length. Halo implantation is usually used to suppress SCE. However, it causes boron pile-up at channel edges and reverse short cannel effect (RSCE) is induced. RSCE can also be induced by transient enhanced diffusion (TED) from S/D implantation damages. Due to complex physics in deep submicron devices, accurate simulation of device and process requires an efficient calibration methodology.
Secondary ion mass spectrometer (SIMS) has been used for basic doping profile calibration. However, SIMS only analyzes one-dimensional doping profiles with strong interference at the interface. Electrical characteristics due to two-dimensional doping profiles cannot be calibrated by SIMS. As a result, threshold voltages were used for detail calibration. In this research, we developed a calibration methodology since the threshold voltage of long channel devices depend only on vertical device structure, long channel devices are calibrated first. Threshold voltages of gate work function, gate oxide thickness and substrate doping profile are used to calibrate. The gate work function can be calibrated by comparing the threshold voltages of n-type and p-type metal-oxide-semiconductor field effect transistors (MOSFETs) with the same n+ poly gate. Threshold voltage with different oxide layers and channel implants are used to extract oxide thickness and substrate doping.
After vertical device structure were calibrated, short channel devices were calibrated for lateral doping profiles. For device without halo-implantation, the roll-up/roll-off of threshold voltage were used to the implant damage and the surface recombination velocity of interstitial. For device with halo implantation, the lateral distribution of implanted profiles was calibrated to match the threshold voltages.
When device structure and doping profiles are calibrated, the mobilities were calibrated I-V curves.
The methodology was applied to calibrate both n-type and p-type support devices for DRAMs. Good agreement was found location simulation and experiment data.
Contents
指導教授推薦書
口試委員會審定書
授權書……………………………………………………………………. III
誌謝……………………………………………………………………….… IV
Figure List……………………………………………….……………… VII
中文摘要……………………………………………….……..…………… XI
Abstract………………………………………………….……………. XIII
Chapter 1 Introduction………………………………………………...1
Chapter 2 Models………………………………………………………...5
2.1 Implant damage model……………………………………….….8
2.2 Pair diffusion model……………………………………..9
2.3 Surface recombination model…………………………..11
2.4 Lombardi surface mobility model…………………....11
Chapter 3 The Calibration Physics and Methodologies…………...14
3.1 Threshold voltage of Long Channel Devices………..14
3.1.1 Work function and gate oxide……………15
3.1.2 Substrate doping……………………………16
3.1.3 Buried channel devices…………………..18
3.2 Calibration methodology for long channel device.20
3.2.1 Calibration of work
function and gate oxide..............20
3.2.2 Calibration of substrate doping…....20
3.2.3 Calibration of buried channel doping.23
3.3 Threshold voltages of short channel devices.....25
3.4 Calibration methodology for short channel devices…......31
3.4.1 The calibration methodology for
reverse short channel effect………...................…31
3.4.2 The methodology for calibration halo implant…………...34
3.5 Calibration methodology for device mobilities………......37
Chapter 4 Simulation and results………………….………………..39
4.1 Grid optimizing……………………………………….…40
4.2 Calibration results of long channel devices…….41
4.3 Calibration results of
short channel n-type MOSFET.....................43
4.4 Result of mobility calibration for
short channel n-type MOSFETs………….…………….51
Chapter 5 Conclusion………………………........……………...…53
Reference
Reference
[1] C. S. Rafferty, et. al., “Explanation of Reverse Short Channel Effect by Defect Gradients” IEDM Technical Digest, 311(1993)
[2] TMA’s TSUPREM IV manual
[3] Neamen, “Semiconductor physics and devices 2nd”
[4] Claudio Lombardi, et. al., “A Physically Based Mobility Model for Numerical Simulation of Nonplanar Devices” IEEE Trans. Computer-Aided Design, vol. 7, No.11, pp. 1164-1170, Nov. 1988.
[5] Yuan Taur, “Fundamentals of MODERN VLSI DEVICES”
[6] C.S. Murthy, “Threshold-voltage Anomaly in Sub-0.2μm DRAM Buried-Channel Devices” VLSI Technology, Systems and Applications, 2001.
[7] Zhi-Hong Liu, “Threshold Voltage Model for Deep-Submicrometer MOSFET’s” IEEE Trans. Electron Devices, vol. 40, p. 86, Jan. 1993
[8] Bin Yu, “Short-Channel Effect Improved by Lateral Channel-Engineering in Deep-Submicronmeter MOSFET’s” IEEE Trans. Electron Devices, vol. 44, pp. 627-634, Apr. 1997
[9] TMA’s MEDICI manual
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