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研究生:韓子非
研究生(外文):T.F Han
論文名稱:CMOS單晶頻率合成器暨振盪器之研究
論文名稱(外文):RF CMOS PLL-based Frequency Synthesizer with On-chip Oscillator
指導教授:江逸群江逸群引用關係
指導教授(外文):Y.C Chiang
學位類別:碩士
校院名稱:長庚大學
系所名稱:半導體科技研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:中文
論文頁數:141
中文關鍵詞:壓控振盪器頻率合成器預除器
外文關鍵詞:VCOFrequency SynthesizerPrescaler
相關次數:
  • 被引用被引用:0
  • 點閱點閱:160
  • 評分評分:
  • 下載下載:45
  • 收藏至我的研究室書目清單書目收藏:1
由於近十年來CMOS在製程上技術的進步,使得它在高頻電路的應用上越來越廣泛.憑藉著其低成本的優勢,高整合度的ICs已逐漸主導了整個通訊市場.在整個收發器電路中,大致可分為Receiver, Synthesizer, Transmitter等三個部分.而必須經由VCO產生之LO訊號,為電路中唯一的訊號源,所以其特性的好壞關係著收發器的優劣.因此擁有低相位雜訊,且能快速鎖定等特點著實為頻率合成器最重要的兩個規格.在此一篇論文中,我將重心主要放在壓控振盪器上之研究,首先我們提出利用改變振盪器之偏壓電流達到改變振盪頻率的方法.在以往之論文中,甚少在這方面上著墨.我們利由閉迴路與開迴路的分析方法,在推導出的公式中,可以觀察出當改變振盪器主動元件的transconductance (gm) 時,其暫態反應對頻率的影響.同時亦能觀察出最好的phase noise工作點區域.論文的第二部分,介紹利用切換共振腔的方法,提供設計雙頻帶壓控振盪器一個新的觀點,以期達到更好的表現.論文的第三部份,主要介紹頻率合成器,除了利用常見的SCL電路,提出差動式預除器的架構之外,其它部分皆與一般作法無異.
Due to the progressive improvement of CMOS process over the past decade, implementation of radio-frequency circuits become relevant. By nature of low cost, high-integration ICs are dominating the communication market. There are three main components, receiver, synthesizer and transmitter comprising the transceiver. Because the LO signal generated by the VCO is the only signal source in the circuits, the performance of the VCO has a profound effect on the transceiver. Fast locking and superior phase noise are indeed the most important specifications of the synthesizer. In this thesis, we focus on the research of the VCOs. First, we introduce the gm-tuning mechanism to change the oscillation frequency of the VCO by changing the bias current of the active devices. Published papers had less researches on this mechanism. Using the closed-loop and open-loop analysis, our derived equation shows the frequency’s transient response of the VCO when changing the transconductance(gm) of the active devices. The operation condition of best phase noise is also concluded. In the second part of the thesis, by using the switched-resonant, we propose a new viewpoint to design the dual-band VCO. In the third part of the thesis, we mainly describe the frequency synthesizer. Using the popular SCL circuits, we design a differential prescaler to improve the immunity to common-mode noise. The remaining components of the synthesizer, except for the VCO, are the same with regular configuration.
Acknowledgements
Abstract
Table of Contents
List of Figures
Chapter 1 Introduction
1.1 Motivation. …………………………………………………………
1.2 RF Frequency Synthesis and Division. …………………………….
1.3 Thesis Organization. ………………………………………………..
Chapter 2 The Principles of Multi-GHz Frequency Synthesizer
2.1 Introduction. ……………………………………………………….
2.2 PLL Fundamentals. ………………………………………………..
2.2.1 Voltage-Controlled Oscillator (VCO). ……………………….
2.2.2 Phase Frequency Detector (PFD). ……………………………
2.2.3 Charge Pump (CP). …………………………………………...
2.2.4 Loop Filter (LPF). …………………………………………….
2.2.5 Frequency Divider . …………………………………………..
2.2.6 Phase Noise Performance Analysis. ………………………….
2.3 Charge-pump PLL design. …………………………………………
2.3.1 Third order PLL. ……………………………………………...
2.3.2 Forth order PLL. ………………………………………………
2.3.3 PLL System-level Behavioral simulation using SIMULINK. ...
Chapter 3 Design of the Voltage-Controlled Oscillator
3.1 Barkhausen''s Criteria and Oscillation Theory. ………………………
3.2 Different Topologies of VCO''s. ………………………………………
3.2.1 Ring Oscillators. ……………………………………………….
3.2.2 Relaxation Oscillators. …………………………………………
3.2.3 LC-tank Oscillators. ……………………………………………
3.3 LC-Tank Oscillators. …………………………………………………
3.3.1 Definition of Q and Phase Noise. ………………………………
3.3.2 Design Issues of LC-tank VCO. ………………………………..
3.4 Implementation of LC-tank VCO’s. ……………………………….
3.4.1 Design of Low Voltage CMOS VCO Using On-chip Varistor. .
3.4.2 Design of Dual-band CMOS VCO Using Switched-resonator. .
3.4.3 Design of 5.8GHz Wide-band VCO With Selectable Bands. …..
Chapter 4 RF CMOS PLL-based Frequency Synthesizer
4.1 Introduction. ………………………………………………………….
4.2 High-frequency Dual-modulus Prescaler. …………………………….
4.2.1 Dynamic Logic Type TSPC Prescaler. …………………………..
4.2.2 Source-coupled Logic (SCL) Type Current Steering Prescaler.
4.3 PLL Building blocks. ………………………………………………….
4.3.1 Complementary CMOS VCO With Noise Filtering Technique. ...
4.3.2 Phase Frequency Detector and Charge Pump. ………………….
4.3.3 Loop Filter. ………………………………………………………
Chapter 5 A 1.8V 5.6GHz Differential Low Noise Frequency Synthesizer . …………………………………………………
5.1 Introduction. …………………………………………………………..
5.2 High-frequency Dual-modulus Prescaler
5.2.1 High-speed Frequency Divider. .......…………………………….
5.2.2 Fully Differential Prescaler. ……………………………………..
5.3 PLL Building blocks. ………………………………………………….
5.3.1 Differential Colpitts VCO With Transformer Design . ………….
5.3.2 Conventional PFD and Differential Charge Pump. ……………..
5.4 Circuits Simulation and Implementation. ……………………………..
Chapter 6 Conclusion and future work
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