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研究生:張書賢
論文名稱:靜態隨機存取記憶體感測放大電路之分析與研究
論文名稱(外文):The analysis and design of SRAM sense amplifier circuits
指導教授:周煌程
學位類別:碩士
校院名稱:長庚大學
系所名稱:半導體科技研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:中文
論文頁數:93
中文關鍵詞:感測放大器記憶體放大器
外文關鍵詞:sense amplifierSASRAMamplifier
相關次數:
  • 被引用被引用:5
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  • 下載下載:208
  • 收藏至我的研究室書目清單書目收藏:1
隨著半導體製程的演進,包含SRAM在內的許多電路系統對於速度、功率消耗與工作電壓的要求愈來愈嚴格,因此本論文針對SRAM中的感測放大器進行研究,以期可以在低工作電壓下依然可以保有快速的操作特性。
本論文提出新型的電流栓鎖式感測放大器與傳統的電流栓鎖式感測電路相較下,從VDD到GND的電晶體級數較少,因此可以在較低的工作電壓下快速的操作。在TSMC 0.35um CMOS製程下以HSPICE模擬,提出之感測放大器在工作電壓1V的情形下,依然擁有100MHz以上的工作頻率,而在改變輸出負載的情況下,提出之感測放大器與傳統電流栓鎖感測放大器及傳統正回授感測放大器相比,感測延遲有6-14%的改善,而功率延遲乘積(PDP)也有14~86%的改善。
另外我們提出之感測放大器應用到256X8 Bits之SRAM中,並且以500MHz的控制訊號為基準,量測SRAM的各個效能參數,除此之外,本論文提出將部份感測放大器的電晶體與行解碼器結合的做法,可以有效的減少感測放大器所占的面積。
As the semiconductor processing technology advances, many VLSI systems including SRAM are requested to work at lower working voltage, lower power consumption and faster speed. Therefore, the main focus of this thesis is on the sense amplifier design of low voltage, low power and high speed SRAM.
A high performance sense amplifier (SA) circuit for low power SRAM applications is presented in this thesis. The transistor stage number of the proposed SA from VDD to GND is reduced for fast low voltage operation. Thus the proposed sense amplifier which is implemented in 0.35um CMOS process can work at 100MHz with voltage as low as 1V. The improvement of sensing delay is 6-14% for various output loading. As the proposed SA works at 3.3V, the simulations show that this design has 14% and 86% power delay product improvement over the prior art and conventional sense amplifier, respectively.
Besides, a solution for the proposed SA to combine with column decoder of SRAM array is demonstrated for low power and high performance applications. Moreover, the proposed SA is applied to the design of a 2k bits SRAM with satisfactory whole chip functions.
目 錄
授權書............................................................................................................................- iii -
誌謝................................................................................................................................- iv -
中文摘要.........................................................................................................................- v -
英文摘要........................................................................................................................- vi -
目錄...............................................................................................................................- vii -
圖目錄.............................................................................................................................- x -
表目錄...........................................................................................................................- xii -
第一章 緒論...................................................................................................................- 1 -
1.1 研究背景.........................................................................................................- 1 -
1.2 研究動機.........................................................................................................- 2 -
1.3 研究方向.........................................................................................................- 2 -
1.3.1 感測放大器之研究方向.........................................................................- 3 -
1.3.2 週邊電路與控制訊號之研究方向.........................................................- 3 -
1.4 章節介紹.........................................................................................................- 4 -
第二章 SRAM架構...........................................................................................................- 6 -
2.1 架構與時序.....................................................................................................- 6 -
2.1.1 輸出入架構說明.....................................................................................- 6 -
2.1.2 操作方式.................................................................................................- 8 -
2.1.3 操作時序.................................................................................................- 9 -
2.2 記憶體電路說明............................................................................................- 11 -
2.2.1 位址轉態偵測電路...............................................................................- 11 -
2.2.2 輸入與輸出暫存器...............................................................................- 16 -
2.2.3 預充電路...............................................................................................- 18 -
2.2.4 寫入電路...............................................................................................- 20 -
2.2.5 列解碼器...............................................................................................- 22 -
2.2.6 行解碼器...............................................................................................- 24 -
2.2.7 記憶單元...............................................................................................- 27 -
2.2.8 感測放大器...........................................................................................- 28 -
2.2.9 三態輸出緩衝器...................................................................................- 29 -
2.3 結論...............................................................................................................- 32 -
第三章 感測放大器設計.............................................................................................- 34 -
3.1 感測放大器簡介............................................................................................- 34 -
3.1.1 功能與設計考量...................................................................................- 34 -
3.1.2 感測放大器分類...................................................................................- 35 -
3.2 傳統感測放大器............................................................................................- 36 -
3.2.1 差動放大器...........................................................................................- 36 -
3.2.2 傳統正回授感測放大器.......................................................................- 37 -
3.2.3 改良式正回授感測放大器...................................................................- 40 -
3.3 電流栓鎖感測放大器....................................................................................- 41 -
3.4 新型電流栓鎖感測放大器............................................................................- 43 -
3.4.1 操作模式分析.......................................................................................- 44 -
3.4.2 面積改善方法.......................................................................................- 46 -
3.5 差動型感測放大器之佈局考量....................................................................- 49 -
3.5.1 輸入點之佈局考量...............................................................................- 49 -
3.5.2 輸出點之佈局考量...............................................................................- 50 -
3.6 結論................................................................................................................- 52 -
第四章 模擬與比較.................................................................................................... - 53 -
4.1 感測放大器的模擬與比較............................................................................- 53 -
4.1.1 感測放大器的模擬環境.......................................................................- 53 -
4.1.2 一般條件下的模擬與比較...................................................................- 55 -
4.1.3 改變輸入負載的模擬與比較...............................................................- 58 -
4.1.4 改變輸出負載的模擬與比較...............................................................- 59 -
4.1.5 改變工作電壓的模擬與比較...............................................................- 61 -
4.2 256X8 Bits SRAM之模擬.............................................................................- 64 -
4.2.1 規格與模擬條件...................................................................................- 64 -
4.2.2 ATD與列解碼電路模擬.......................................................................- 64 -
4.2.3 讀取操作模擬.......................................................................................- 66 -
4.2.4 寫入操作模擬.......................................................................................- 67 -
4.2.5 ATD訊號變異模擬...............................................................................- 69 -
4.2.6 量化模擬結果整理...............................................................................- 71 -
4.2.7 感測放大器在2K SRAM中的應用.....................................................- 72 -
4.3 結論................................................................................................................- 73 -
第五章 總結與建議.....................................................................................................- 74 -
5.1 總結................................................................................................................- 75 -
5.2 建議未來研究方向........................................................................................- 76 -
參考文獻.......................................................................................................................- 77 -
附件一 2K Bits SRAM Layout....................................................................................- 80 -
附件二 2K Bits Schematic...........................................................................................- 81 -
附件三 英文稿….........................................................................................................- 90 -
圖 目 錄
圖2.1 本論文所使用之SRAM架構圖.........................................................................- 7 -
圖2.2 本論文所使用之SRAM操作時序圖...............................................................- 10 -
圖2.3 ATD電路架構示意圖.....................................................................................- 12 -
圖2.4 ATD操作時序模擬圖.....................................................................................- 14 -
圖2.5 XOR閘之基本電路圖.....................................................................................- 15 -
圖2.6 分叉輸出栓鎖器圖........................................................................................- 16 -
圖2.7 暫存器之工作時序圖....................................................................................- 17 -
圖2.8 預充電路圖....................................................................................................- 18 -
圖2.9 寫入電路與位元線配置圖............................................................................- 20 -
圖2.10 寫入電路圖....................................................................................................- 21 -
圖2.11 列解碼器邏輯電路圖....................................................................................- 23 -
圖2.12 列解碼器電路圖............................................................................................- 24 -
圖2.13 行解碼器電路圖............................................................................................- 25 -
圖2.14 6T之SRAM記憶單元電路圖..........................................................................- 27 -
圖2.15 感測放大器工作簡圖....................................................................................- 29 -
圖2.16 三態輸出緩衝器圖........................................................................................- 29 -
圖2.17 本論文提出與採用之三態輸出緩衝器圖....................................................- 31 -
圖3.1 傳統感測放大器電路圖................................................................................- 36 -
圖3.2 傳統正回授感測放大器電路圖....................................................................- 38 -
圖3.3 正回授感測放大器模型圖............................................................................- 38 -
圖3.4 改良式正回授感測放大器電路圖................................................................- 40 -
圖3.5 電流栓鎖感測放大器圖................................................................................- 42 -
圖3.6 本論文所提出的新型電流栓鎖感測放大器電路圖....................................- 44 -
圖3.7 新型感測放大器操作在預充模式(SE=0)的示意圖....................................- 45 -
圖3.8 新型感測放大器操作在感測模式(SE=1)的示意圖....................................- 46 -
圖3.9 感測放大器佈局圖........................................................................................- 48 -
圖3.10 新型感測放大器與行解碼器結合圖............................................................- 49 -
圖3.11 感測放大器輸入端之佈局考量圖................................................................- 50 -
圖3.12 感測放大器輸出負載與阻抗關係示意圖....................................................- 51 -
圖3.13 感測放大器輸出點佈局示意圖....................................................................- 51 -
圖4.1 感測放大器的模擬環境圖............................................................................- 54 -
圖4.2 新型感測放大器工作在一般條件之模擬波型圖........................................- 56 -
圖4.3 感測放大器改變輸入負載之模擬波形圖....................................................- 58 -
圖4.4 H.S.D與輸入負載的關係圖.........................................................................- 59 -
圖4.5 感測放大器改變輸出負載之模擬波形圖....................................................- 60 -
圖4.6 H.S.D與輸入負載的關係圖.........................................................................- 60 -
圖4.7 感測放大器在工作電壓1V時的模擬結果圖...............................................- 62 -
圖4.8 H.S.D與工作電壓關係圖.............................................................................- 62 -
圖4.9 PDP-H與工作電壓關係圖.............................................................................- 63 -
圖4.10 SRAM ATD訊號與列解碼器模擬圖................................................................- 65 -
圖4.11 SRAM 讀出操作之模擬圖..............................................................................- 66 -
圖4.12 SRAM 寫入操作之模擬圖..............................................................................- 68 -
圖4.13 ATDCLK與Select訊號圖..............................................................................- 69 -
圖4.14 ATDCLK與 隨位址變化增加的改變量模擬....................................- 70 -
圖4.15 ATDCLK與 隨位址變化增加的改變關係圖....................................- 70 -
圖4.16 2K SRAM再讀出操作時各動作所佔時間之比例圖......................................- 72 -
表 目 錄
表3.1 感測放大器的分類........................................................................................- 35 -
表3.2 電晶體大小與數量比較表............................................................................- 47 -
表4.1 各感測放大器在一般條件下佈局前模擬的結果比較表............................- 56 -
表4.2 各感測放大器在一般條件下佈局後模擬的結果比較表............................- 57 -
表4.3 本論文所研究之2K bits SRAM 規格表.......................................................- 71 -
表4.4 本論文所研究之2K bits SRAM 整體效能表...............................................- 71 -
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