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研究生:劉彥宏
研究生(外文):Yen-Hung Liu
論文名稱:雙頻帶射頻前端電路之研製
論文名稱(外文):Design of Dual-Band RF Front-End Integrated Circuits
指導教授:馮武雄馮武雄引用關係鄭瑞清
指導教授(外文):Wu-Shing FengJui-Ching Cheng
學位類別:碩士
校院名稱:長庚大學
系所名稱:半導體科技研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:中文
論文頁數:125
中文關鍵詞:低雜訊放大器壓控振盪器平面式天線雙頻帶
外文關鍵詞:Low noise amplifierVoltage-controlled oscillatorPatch antennaDual-band
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本論文使用TSMC 0.18µm 1P6M CMOS製程來實現一個應用於IEEE 802.11a與IEEE 802.11b WLAN之雙頻帶射頻前端電路,將兩個頻帶整合在一個晶片上,不但低功率省電,IC面積小與單電壓易於整合。而且近年來CMOS RFIC的快速發展使整合基頻與射頻電路實現單系統晶片(SoC:System on a Chip)的製作可行,因此可大量降低成本。
在本論文中,實現可變增益雙頻帶低雜訊放大器操作在1.5 V的電壓並工作在兩種不同的增益和雜訊指數的模式下量測結果為在高增益模式時,2.4GHz增益為5.72dB,雜訊指數為5.55dB,5.8GHz增益為1.68dB,雜訊指數為9.39dB。在低增益模式時,2.4GHz增益為2.25dB,雜訊指數為5.7dB,5.8GHz增益為-5.67dB,雜訊指數為9.53dB。5.8GHz CMOS電流共用低雜訊放大器量測結果增益為8.45dB,雜訊指數為4.82dB以及2.4GHz CMOS差動式低雜訊放大器模擬結果增益為15.66dB,雜訊指數為2.32dB;四相位輸出壓控振盪器輸出頻率為2.898-3.177GHz,相位雜訊-110.4dBc/Hz@1MHz,可調範圍279MHz。電路是使用安捷倫Agilent Eesoft EDA-ADS模擬軟體及TSMC 0.18μm 1P6M CMOS製程來完成。
This thesis presents the development of IEEE 802.11a and IEEE 802.11b concurrent dual-band RF front-end circuits in TSMC(Taiwan Semiconductors Manufacture Company) standard 0.18μm CMOS technology. By integrating the two-band circuit, the cost of manufacturing, the power consumption and chip size are reduced. Recent development of CMOS RF IC design allows the realization of the concept of System on a Chip(SOC) consisting of three functional blocks: radio-frequency, intermediate-frequency and baseband-frequency circuits. Therefore, the cost is reduced considerably.
In the thesis, 1.5V dual-band variable gain low noise amplifier(DBVG-LNA) are designed and fabricated. The DBVG-LNA has two operating modes. In the high gain mode, 5.72dB gain and 5.55dB noise figure are achieved at 2.4GHz while 1.68dB gain and 9.39dB noise figure are achieved at 5.8GHz. In the low gain mode, 2.25dB gain and 5.7dB noise figure are achieved at 2.4GHz while —5.67dB gain and 9.53dB noise figure are achieved at 5.8GHz. The 5.8GHz CMOS current-reuse LNA has 8.45dB gain and 4.82dB noise figure. The 2.4GHz CMOS differential LNA has 15.66dB gain and 2.32dB noise figure. The LC-tank VCO has an output frequency range from 2.898 to 3.177GHz with phase noise -110.4dBc/Hz at 1MHz and tuning range 279MHz. The schematics and elements of front-end are simulated by Agilent’s EDA(Electronic Design Automatic)-ADS(Advanced Design System)RF IC Designer
第一章 導論…………………………………………………… 1
1.1 研究動機……………………………………………… 1
1.2 論文架構……………………………………………… 5
第二章 CMOS 無線接收端之系統架構………………………… 7
2.1 簡介…………………………………………………… 7
2.2 超外差式接收機架構………………………………… 9
2.3 直接降頻式接收機架構……………………………… 12
2.4 映像拒斥接收機架構………………………………… 17
2.5 低中頻接收機架構…………………………………… 22
2.6 同時接收之雙頻帶接收機架構……………………… 23
第三章 射頻接收端電路的考量與元件簡介………………… 25
3.1 簡介…………………………………………………… 25
3.1.1 增益…………………………………………………… 26
3.1.2 雜訊指數……………………………………………… 28
3.1.3 非線性度……………………………………………… 32
3.2 TSMC 0.18µm 1P6M CMOS元件簡介………………… 36
3.2.1 NMOS電晶體…………………………………………… 36
3.2.2 MIM電容……………………………………………… 37
3.2.3 MOS可變壓控電容…………………………………… 38
3.2.4 螺旋式電感…………………………………………… 39
3.2.5 鎊線…………………………………………………… 40
第四章 CMOS低雜訊放大器之分析與實現…………………… 41
4.1 簡介…………………………………………………… 41
4.2 CMOS低雜訊放大器基本架構與原理………………… 43
4.2.1 低雜訊放大器的基本架構…………………………… 43
4.2.2 雜訊模型分析………………………………………… 46
4.3 可變增益雙頻帶CMOS低雜訊放大器設計與製作…… 53
4.4 可變增益雙頻帶低雜訊放大器模擬與量測結果比較 56
4.5 5.8 GHz CMOS電流共用低雜訊放大器設計與製作… 69
4.6 5.8 GHz CMOS電流共用低雜訊放大器模擬與量測結果比較………………………………………………………………… 72
4.7 2.4 GHz CMOS差動式低雜訊放大器設計與製作…… 79
4.8 2.4 GHz CMOS差動式低雜訊放大器模擬與量測結果比較…………………………………………………………………… 82
第五章 CMOS壓控振盪器……………………………………… 86
5.1 簡介…………………………………………………… 86
5.2 CMOS震盪器工作原理………………………………… 87
5.3 CMOS四相位正交輸出壓控震盪器之設計與製作…… 104
5.4 CMOS四相位正交輸出壓控震盪器模擬結果………… 107
第六章 結果與討論…………………………………………… 111
參考文獻…………………………………………………………… 113
附錄A 雙頻帶平面型天線之設計與實現…………………… 118
A.1 簡介…………………………..……………………… 118
A.2 平面式天線的設計…………………………………… 119
A.3 平面式天線的模擬與量測結果……………………… 120
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