臺灣博碩士論文加值系統

我們已經發展出一個簡單方法形成高介電係數的氧化鑭閘極，就是沉積鑭薄膜再直接熱氧化。由於應用低氧化溫度，減少氧化鑭厚度使介電質完整地改善。 從測量電容值，這 60 Å的氧化鑭有27的K值，它的等效氧化層厚度是8.7Å。從 MOSFET's 的高電流驅動和轉移電導隨著低的off-state的電流進一步證據高介電質的長遠性。它被發現與二氧化矽比起來有低應力引發的漏電流(SILC)和高電荷崩潰，它被證實有極好可靠性。那低的等效氧化物厚度是由於在矽上的高熱力穩定性以及用氫氣穩定的在550oC以下退火。
同時我們也發展出成長磊晶矽鍺合金的新方法。這方法主要是藉由固相磊晶法將沈積在矽基板上的無晶狀錯層在高溫下趨入並形成矽鍺磊晶層。我們發現晶片表面殘存原生氧化層的存在與否對於矽鍺層的品質有重大的影響。為了評估此矽鍺層應用於實際元件的可行性，我們做了以矽鍺為通道的電晶體。然而，這樣的結果和以往的文獻記載並不相同，我們推測這樣的差異是因為此方法形成的矽鍺層已是應力釋放過的材料。因此，並不會有應力在高溫氧化釋放造成缺陷的現象。儘管如此,此矽鍺層氧化層仍會因錯原子累積在氧化層和矽鍺介面而造成其介面缺陷密度稍高於傳統的二氧化矽。
因此我們也將結合上述成長閘極氧化層與矽鍺層的技巧，來應用於P型電晶體的通道,其展現了較好的電流,驅動力與次臨界特性。這項技術的優點不僅在於其簡單,經濟,最重要的是它完全相容於現有的積體電路製程技術。
未來隨著元件尺寸的不斷縮小，閘極氧化層的厚度也必須隨之減少。原來的閘極氧化層的厚度可能到一個臨界值，我們也正在研究以細胞為介電材料的可行性而做了一系列的細胞與電場之間相關的研究。

We have developed high K La2O3 gate dielectrics by a simple process using direct thermal oxidization of deposited La. The dielectric integrity improves as decreasing La2O3 thickness because of the applied low oxidation temperature. From the measured capacitance, the 60Å La2O3 has a K value of 27 that has an equivalent oxide thickness of 8.7Å. This high K is further evidenced from MOSFET’s high current drive and transconductance with low off-state current. Low stress-induced leakage current and high charge-to-breakdown comparable with SiO2 are obtained that demonstrates excellent reliability. The achieved low equivalent oxide thickness is due to the high thermodynamic stability on Si and also stable for hydrogen annealing up to 550oC.
At the same time, it is developed a new approach to form epitaxial SiGe layer .The epitaxial SiGe was formed by the deposition of amorphous Ge layer and subsequent high temperature annealing through the mechanism of solid phase epitaxy. It was found that the existence of native oxide plays a critical role in the quality of SiGe layer. To evaluate the feasibility of this SiGe layer in practical applications, we have fabricated SiGe channel MOSFET's. However, this result is much different from that in the previous reporters. SiGe layer formed in this method is a relaxed material and may not suffer from the strain-relaxation related problems in the high temperature oxidation step.
Therefore, we have successfully integrated two techniques into current VLSI technology to fabricate SiGe cham1el PMOSFET's with high k dielectric. It manifests batter current drive capability and batter subthreshold swing. More important, this approach is simple, less expensive and fully compatible with current VLSI tech1ology.
In the future, according to the continuous scaling down of device, the thickness of gate oxide has to be reduced. The thickness of gate oxide will be decreased to the limitation. It also has been investigated into the feasibility of the biological cell, in order to substitute for gate dielectric. Then it is experimenting with the relationship between the cell and the electric field.

Contents
Abstract (in Chinese)………………………………………i
Abstract (in English) ………………………………iii
Acknowledgement…………………………………………v
Contents……………………………………………………vi
Figure Captions………………………………………vii
Chapter 1 Introduction
1.1 High K Gate Dielectrics in La2O3/Si0.3Ge0.7MOSFET……1
1.2 Cell Membranes in Biological Cells…………………5
Chapter 2 Experimental
2.1 La2O3/Si0.3Ge0.7 p-MOSFETs …………………………11
2.2 Process for Deep Trench Array Structure…………………12
Chapter 3 Results and discussion
3.1High K Gate Dielectrics in La2O3/Si0.3Ge0.7 p-MOSFET...16
3.2 Biological Cells………………………………….19
Chapter 4
Conclusion................21
Figure.3.1-Figure.3.12....................23
References.................................39

[1.1]K. Rim, J .Welser, J. L. Hoyt and J. F.Gibbons, "Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs," Electron Devices Meeting, pp. 517-520, 1995.
[1.2]K. Ismail, J. O. Chu and B. S. Meyerson, “High hole mobility in SiGe alloys for device applications,” Appl. Phys. Lett. 64, 3124 ,1994.
[1.3]D. K. Nayak, J. C. S. Woo, J.S. Park, K. L. Wang, and K. P. Mac Williams, “High-mobility p-channel metal-oxide-semiconductor field-effect transistor on strained Si,” Appl. Phys. Lett. 62, pp. 2853, 1993.
[1.4]D. K. Nayak, J. C. S. Woo, G. K.Yabiku, K. P. Mac Williams, J.S. Park and K. L. Wang, “High-mobility GeSi PMOS on SIMOX ,” IEEE Electron Devices Lett. 14, pp. 520-522, 1993.
[1.5]W. Bin, J. S. Suehle, E. M. Vogel and J. B. Bernstein, “Time-dependent breakdown of ultra-thin SiO2 gate dielectrics under pulsed biased stress,” IEEE Electron Device Lett. 22, pp. 224-226, 2001.
[1.6]J. H. Stathis, A. Vayshenker, P. R. Varekamp, E. Y. Wu, C. Montrose, J. McKenna, D. J. DiMaria, L. -K. Han, E. Cartier, R. A. Wachnik and B. P. Linder,Breakdown measurements of ultra-thin SiO2 at low voltage,” IEDM Tech. Dig., pp. 94-95, 2000
[1.7]M. Koyama, K. Suguro, M. Yoshiki, Y. Kamimuta, M. Koike, M. Ohse, C. Hongo and A. Nishiyama, “Thermally stable ultra-thin nitrogen incorporated ZrO2 gate dielectric prepared by low temperature oxidation of ZrN,” IEDM Tech. Dig., pp. 20.3.1-20.3.4, 2001
[1.8]E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A. Gribelyuk, H. Okorn-Schmidt, C. D Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L. A. Ragnarsson and Rons, “Ultrathin high-K gate stacks for advanced CMOS devices,” IEDM Tech. Dig., pp. 20.1.1-20.1.4, 2001
[1.9]J. A. Lundqvist, F. Sahlin, M. A. I. Åberg, A. Strömberg, P. S. Eriksson, and O. Orwar, “Altering the biochemical state of individual cultured cells and organelles with ultramicroelectrodes,” The National Academy of Sciences , vol.95, pp. 10356-10360 ,September 1998.
[1.10]A. Chin, C. C. Liao, C. H. Lu, W. J. Chen, and C. Tsai, “Device and Reliability of High-K Al2O3 Gate Dielectric with Good Mobility and Low Dit,” Symp. on VLSI Technology, p.133-134, Japan, June 1999.
[2.1] Y. H. Wu and A. Chin,"High-temperature formed SiGe p-MOSFETs with good device characteristics,” IEEE Electron Device Lett., vol. 21,pp. 350—352, July 2000.
[2.2]“Gate oxide integrity of thermal oxide grown on high temperature formed Si Ge ,” IEEE Electron Device Lett., vol. 21, pp. 113—115,
Mar. 2000.
[2.3] Y. H. Wu, A. Chin, and W. J. Chen, “Thickness-dependent gate oxide quality of thin thermal oxide grown on high-temperature formed SiGe,”IEEE Electron Device Lett., vol. 21, pp. 289—291, June 2000.
[2.4] C. Y. Lin, W. J. Chen, C. H. Lai, A. Chin, and J. Liu, “Formation of Ni germano-silicide on single crystalline Si Ge /Si,” IEEE Electron Device Lett., vol. 23, no. 8, pp. 464—466, 2002.
[2.5] C. Salm, J. H. Klootwjik, Y. Ponomarev, P. W. M. Boos, D. J.Gravestejin,and P. H. Woerlee, “Gate current and oxide reliability in poly MOS capacitors with poly-Si and poly-Si Ge .” IEEE Electron Device Lett., vol. 19, pp. 213—215, July 1998.