臺灣博碩士論文加值系統

隨著時代的進步，網路以經變成多數人每天當中不可或缺的一部份。資訊化的生活多半會與網路相結合，網路可以提供各式各樣不同的資訊與服務。而隨著網路能提供的功能越多，就會有越多的資料在網路上傳送。當然，在這些資料中一定包含著某一些重要的資料，假若沒有適當的資料保密機制，這些重要的資料可能被有心人士所取得。所以網路安全這個領域也慢慢的被重視，很多新的保密機制也因此而被發展。
在這篇論文之中，主要也是將希望能夠設計一系統單晶片平台，並且加入資料加密的機制，使得需要透夠網路傳輸資料的系統，能夠藉由加入這個設計來提高資料在傳輸時的安全性。在篇論文中，主要以ALTERA所提供的開發環境來作系統開發，再配合DES電路的設計來構成整篇論文的重心。論文中將提出三種不同的架構來實作這個加解密系統。這三種架構分別是，第一種是完全以軟體的方式來處理加解密系統的運作，第二種是以第一種架構為根本再加上以altera所提供的custom instruction方式為cpu加上訂製的硬體電路來加速加解密的運算，第三種則是利用一個客製的wrapper來將des的硬體電路直接掛載到系統匯流排上，直接以硬體電路的方式來執行加解密。經由這三種不同的架構，我們可以了解在不同架構下加解密系統的執行效能為何，以及每個架構所需的硬體空間為何。

As the time goes on, network has already become a part of our daily life. The life with information technology almost combines with network, and network can provide various kinds of information and service. As the network provides more and more services, there will be more and more data transmitted through the network. Of course, there must be some important information transmitted through the network. If we do not have good security system, and someone may steal those important data, easily. So, more and more people pay attention to the area, network security, and a lot of new secrecy mechanism have been developed.
In this thesis, I want to develop a SOC platform with data encryption/decryption mechanism. With this system design, it can provide higher data transmission security for the systems that must transmit information through the network. In this thesis, I will use a system development tool that provided by ALTERA to development system, and DES circuit design to construct the main point of this thesis. I will propose three different architectures to implement this data encryption/decryption system. In the architecture1, the data encryption/decryption operation is done by software. In architecture2, we use custom instruction to add additional hardware instruction to speedup the DES data encryption/decryption operation. The last architecture will use a customized hardware to accomplish the data encryption/decryption operation. In this architecture, the first work is designing a DES circuit, and then is writing a wrapper to connect the DES circuit and the original architecture. These three different architectures let us know the performance, and the hardware space of each kind of architecture.

Table of Contents
Acknowledgementi
摘 要ii
Abstractiii
Table of Contentsiv
List of Figuresv
List of Tablesvii
Chapter 1 Introduction1
Chapter 2 Background3
2.1 Embedded Systems3
2.2 Cryptology System7
2.3 Network Transmission15
2.4 Cryptography Application on Network Transmission26
2.5 ALTERA SOPC platforms29
Chapter 3 System Architecture37
3.1 Architecture1 — Pure Software Execution Architecture39
3.2 Architecture2 — Using Custom Instruction to speed up soft code DES operation41
3.3 Architecture3 — Using wrapped DES circuit to replace the soft code DES operation44
Chapter 4 System Implementation and Performance Evaluation46
4.1 Implementation46
4.2 Performance Evaluation67
4.3 Performance Analysis69
Chapter 5 Conclusion and Future work71
5.1 Conclusion71
5.2 Future work72
References73
Resume of Author74


List of Figures
Figure 2.1：Traditional Cryptology System8
Figure 2.2：Private Key Cryptosystem9
Figure 2.3：Data Encryption steps12
Figure 2.4：Hardware for one DES round12
Figure 2.5：In each round, a sub-key has been generated12
Figure 2.6：Basic Architecture of TDES13
Figure 2.7：OSI 7 Layers17
Figure 2.8：Data Encapsulation18
Figure 2.9：The TCP/IP model.19
Figure 2.10：Comparing TCP/IP with OSI 7 layers.20
Figure 2.11：MAC Address Format22
Figure 2.12：IP Address Classes23
Figure 2.13：Ethernet and IEEE 802.3 Frame Format24
Figure 2.14：Security Mechanism’s corresponding position in TCP/IP27
Figure 2.15：SSL’s Protocol Layer27
Figure 2.16：NIOS Development Board30
Figure 2.17：Embedded Software Design Tool Flow34
Figure 3.1：Software System Architecture37
Figure 3.2：System Hardware Architecture37
Figure 3.3：Data Encryption steps39
Figure 3.4：Architecture_1…Pure Software Execution Architecture40
Figure 3.5：Adding Custom Logic to the Nios ALU42
Figure 3.6： Architecture2 — Use Custom Instruction to speed up soft code DES operation43
Figure 3.7：Hardware for one DES round44
Figure 3.8：Architecture3 — Use wrapped DES circuit to replace the soft code DES operation45
Figure 4.1：Entirely System Overview46
Figure 4.2：NIOS Tool Flow47
Figure 4.3：Quartus and NIOS processor block diagram.49
Figure 4.4：The SOPC Builder starting figure.50
Figure 4.5：SOPC Builder components configuration figure.51
Figure 4.6：More settings of NIOS processor51
Figure 4.7：System Generation messages.52
Figure 4.8：Add new processor core into the system design.53
Figure 4.9：System design compilation53
Figure 4.10：Coding DES application54
Figure 4.11：Code translating steps55
Figure 4.12：Making the ROMDISK file56
Figure 4.13：NIOS Processor configuration figure.57
Figure 4.14：Custom instruction part in the window.58
Figure 4.15：Interface to User Logic window.58
Figure 4.16：Custom Instruction clock cycle setting.59
Figure 4.17：FPGA Advantage tool window.61
Figure 4.18：Second level block diagram of the Wrapped-DES circuit design.62
Figure 4.19：Block diagram of the DES circuit design.62
Figure 4.20：Write circuit of the wrapper design.63
Figure 4.21：Read circuit of the wrapper design.64
Figure 4.22：Modelsim tool window and testbench file.64
Figure 4.22：ModelSim Simulation Waveform.65
Figure 4.23：Adding the Wrapped-DES design into the processor design.66
Figure 4.24：3 different position of the user logic.69

List of Tables
Table 2.1：The APEX20K200E Device Features30
Table 2.2：The Flash memory allocation.31
Table 4.1：Hardware Specification of each Architecture67
Table 4.2：Comparison of two architectures68

[1] Chi Sung Laih, Lein Harn, Chin Chen Chang, “Contemporary Cryptography and its Applications,” Summer, 1995, UNALIS, INC
[2] William Stallings, “ Cryptography and Network Security — Principles and Practice,” Second Edition, 1999, PRENTICE HALL, INC
[3] Brent E. Nelson, “Reconfigurable Computing：An Introduction and Overview” Brigham Young University September 23, 1998
[4] William Stallings, “ Data and Computer Communications,” Fifth edition, 1997, PRENTICE HALL
[5] NIOS related information supported by ALTERA. http://www.altera.com/products/devices/nios/nio-index.html
[6] uClinux Operating System related information supported by Microtronix. http://www.microtronix.com/
[7] CIC Training Manual, “Altera Training Course for PC Users,” Andr´ e DeHon and John Wawrzynek
[8] CIC Training Manual, “Reconfigurable Computing:What, Why, and Implications for Design Automation,” Berkeley Reconfigurable, Architectures, Software, and Systems Computer Science Division, University of California at Berkely
[9] 梁均皓“以多層式感知器為基礎的可重組式類神經網路架構,”逢甲大學資訊工程系碩士班論文,2002年6月.