臺灣博碩士論文加值系統

功率消耗在傳統的VLSI晶片設計上通常是不被重視的一個焦點，但是隨著現今製作超大型積體電路的技術不斷的提升，而且對於晶片的功能要求越來越高，以至於使得降低電路的功率消耗反而成為一個棘手的問題。因此目前有許多降低功率的技術不斷的被提出來，當這些技術不斷的出現的時候，最需要的就是一個有效率、正確性高的評估方式，因此評估功率消耗也成為其中重要的一個環節。
在這一論文中我藉著回歸分析替電路建立有效率的功率消耗模型(power model)，希望可以有助於提升開發設計電路的時間。

第一章 簡介
1.1 研究動機
1.2 內容大綱
第二章 背景知識
2.1 功率評估的技術
2.2 RT-Level的功率評估
第三章 理論與架構
3.1 功率巨集模型
3.2 以方程式為基礎的巨集模型
3.3 Recursive least square 演算法
3.4 模型的建立流程
第四章 實驗結果
第五章 結論
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