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研究生:賴勝坤
研究生(外文):Sheng -Kun Lai
論文名稱:2.4GHzCMOS鎖相迴路
論文名稱(外文):2.4GHz CMOS Phase-Locked Loop
指導教授:張振豪
指導教授(外文):Robert C.Chang
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:中文
論文頁數:62
中文關鍵詞:2.4GHz鎖相迴路相位頻率檢知器電荷幫浦低通濾波器壓控振盪器除頻器
外文關鍵詞:2.4GHz phase-locked loopphase/frequency detectorcharge-pumplow-pass filtervoltage-controlled oscillatorfrequency divider
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本篇論文研究一個2.4GHz鎖相迴路,它包含著相位頻率檢知器(PFD)、電荷幫浦(Charge pump),低通濾波器(LPF)、壓控振盪器(VCO)、除頻器(Frequency Divider),這一個鎖相迴路可以用在無線通信系統,提供內部振盪頻率。
所設計鎖相迴路,其相位頻率檢知器,是用動態邏輯閘組成具有無dead zone的特性,可偵測外部號參考信號和除頻後的信號,當兩個信號比較相位差之後,相位頻率檢知器可以產生足夠寬度的up或down脈衝信號,供給電荷幫浦產生控制電壓,調整壓控振盪器的頻率。正回授CMOS 電荷幫浦,以對稱的電路來設計,具有正回授可增加交換速度的電荷幫浦,正回授及電流的再利用是被用來加快交換速度和低功率消耗,電荷幫浦可將偵測出來的相位差轉換成相對的電壓差,用來調變電壓控制壓控振盪器的振盪頻率。低通濾波器是用二階RC電路組成,用途在濾掉電荷幫浦所輸出的高頻成分。壓控振盪器是採用環形振盪器架構,由CMOS差動對組成delaycell,接受控制信路號調變delaycell的延遲時間,以調變輸出頻率,它的振盪頻率範圍是在1.75GHz~2.6GHz。除頻器是用到比例邏輯技術的TSPC動態正反器,達到快速除頻的要求。
整個2.4GHz頻率合成器系統的電源是2.8V,當控制電壓到1.82V時即可鎖住頻率為2.4GHz,鎖住時間為8μs,消耗功率為44.7mW,使用TSMC 0.35μm CMOS 1P4M 的製程技術來模擬與製作,晶片面積為221μm×71μm(不含R、C及IO Pad)。

In this thesis, a 2.4GHz CMOS phase-locked loop is designed,it is composed of a phase/frequency detector(PFD),a charge-pump(CP),a low-pass filter(LF),a voltage-controlled oscillator(VCO)and a frequency divider(FD).This frequency synthesizer can be employed in the wireless communication system to provide the internal oscillation frequency.
In the proposed phase-locked loop,the phase/frequency detector is made up of dynamic logic gates and without dead zone.The PFD can detect the phase and frequency error of the reference frequency and the divider output.After the two signals are compared,in the PFD, enough width of the up or down impulse signal is produced and sent to the CP,which produces a controlled voltage to adjust the frequency of the VCO.The positive feedback CMOS CP is designed by the symmetrical circuit,the CP with positive feedback can increase charging speed,and reuse of current can reduce power consumption.The CP transforms the phase and frequency error into a relative voltage difference to change the frequency of the VCO.The function of the second-order LF is composed of R and C and is to filter the high frequency component of the output signal of the CP.The VCO employs the ring-oscillator structure.The delay-cell consists of CMOS differential-pair and changes the delay time by the control voltage,to adjust the frequency of the VCO.The frequency of the VCO is 1.75GHz ~2.6GHz.The FD employs TSPC dynamic D flip-flop with ratio logic technique,to quickly achieve the request of the frequency dividing.
The supply voltage of the 2.4GHz CMOS phase-locked loop is 2.8V.The locking frequency is 2.4GHz when the controlled voltage is 1.82V.The locking time is 8μs,and power consumption is 44.7mW.This phase-locked loop is simulated and implemented by TSMC 0.35 μm CMOS 1P4M technology.The chip area is 221μm ×71μm(not including R、C and IO Pads).

目錄
摘要……………………………………………………………………….ⅰ
Abstract………………………………………………………………...ⅱ
誌謝……………………………………………………………………….ⅳ
目錄……………………………………………………………………….ⅴ
圖目錄…………………………………………………………….………ⅶ
表目錄…………………………………………………………………….ⅹ
目錄
第一章 緒論
1. 1研究動機………………………………………………………1
1.2 研究方法與流程………………………………………………2
1.3 內容大綱………………………………………………………2
第二章 鎖相迴路(PLL)的基本觀念
2.1 鎖相迴路(PLL)的基本原則………………………………4
2.2 二階鎖相迴路(Second-order PLL)……………………….9
2.3 三階鎖相迴路(third-order PLL)…………………………10
2.4 鎖相迴路應用於頻率合成器(PLL based frequency synthesizer)
……………………………………………………………………12
2.5 鎖相迴路應用於資料和時脈回復器(Data and clock recovery by PLL)…………………………………………………………….14
2.6 Jitter and skew抑制………………………………………….15
第三章 鎖相迴路的組成電路:相位頻率檢知器、電荷幫浦、低通濾波器、壓控振盪器、除頻器的設計
3.1相位頻率檢知器(phase frequency detector)…………….17
3.1.1相位頻率檢知器的觀念………………………………...17
3.1.2 相位頻率檢知器的基本電路………………………… .19
3.1.3 相位頻率檢知器的改進…………………………….….20
3.1.4 相位頻率檢知器的實際電路…………………………..22
3.2 電荷幫浦(charge pump)…………………………………….26
3.2.1 電荷幫浦的觀念………………………………….….….27
3.2.2 傳統的電荷幫浦………………………………….……..28
3.2.3 實際的電荷幫浦電路…………………………….……..29
3.3 迴路濾波器……………………………………………….….…36
3.4 壓控振盪器(voltage controlled oscillator)…………….….…38
3.4.1 壓控振盪器的性質……………………………………….39
3.4.2 傳統的環形振盪器…………………………………….…40
3.4.3 2.4GHz四輸入差動delay cell 壓控振盪器………42 3.4.4 本論文所提出的2.4GHz壓控振盪器………………….45
3.5 除頻器(frequency divider)…………………………………..48
3.5.1除頻器的性質……………………………………………..48
3.5.2 除2的除頻器…………………………………………….52
3.5.3 除8的除頻器…………………………………………….53
第四章 鎖相迴路的模擬……………………………………………..56
4.1 鎖相迴路模擬的結………………………………………….56
第五章 結論(conclusion)………………………………….…….60
參考文獻………………………………………………………………….61
圖目錄
圖2.1 鎖相迴路基本頻率合成器系統電路方塊……………………...4
圖2..1.1 鎖相迴路系統電路方塊………………………………………5
圖2.1.2 鎖相迴路系統的線性模型…………………………………….7
圖2.2.1二階鎖相迴路電路方塊圖………………………………………9
圖2.3.1三階鎖相迴路電路方塊圖………………………………………11
圖2.4.1 鎖相迴路基本頻率合成器系統電路方塊……………………12
圖2.4.2 PFD輸入(R、V)與輸出(U、D)的時序圖…………….13
圖2.4.3鎖相迴路應用於頻率合成器,除頻器是必須的………………13
圖2.5.1 鎖相迴路應用於資料和時脈回復器電路方塊………………15
圖2.6.1 Cycle jitter…………………………………………………,…..15
圖2.6.2 skew現象……………………………………….…………,….16
圖3.1.1相位頻率檢知器的方塊圖…………………………………,…..17
圖3.1.2相位頻率檢知器的狀態圖…………………………………,…..18
圖3.1.3 相位頻率檢知器的輸入信號(R、V)和輸出信號(U、D)18圖3.1.4 傳統相位頻率檢知器的電路架構圖………………………….19圖3.1.5 傳統相位頻率檢知器的時序圖………………………………..19
圖3.1.6 改良型相位頻率檢知器的架構………………………………..21圖3.1.7 改良型相位頻率檢知器的時序圖……………………………..22
圖3.1.8 傳統的相位頻率檢知器電路…………………………………..23
圖3.1.9 動態式的D型正反器………………………………………….23
圖3.1.10 具有無dead zone的動態式相位頻率檢知器………………..24
圖3.1.11當ref相位領先local時,動態式相位頻率檢知器各點波形25
圖3.1.12當ref相位落後local時,動態式相位頻率檢知器各點波形26圖3.2.1 電荷幫浦的簡單模型…………………………………………..27
圖3.2.2電荷幫浦和相位頻率檢知器的轉移曲線……………………..28
圖3.2.3 傳統的電荷幫浦電路………………………………………….29
圖3.2.4改良的電荷幫浦基本電路……………………………………..30
圖3.2.5 修正後的電荷幫浦……………………………………….……31
圖3.2.6 具有正回授可增加交換速度的電荷幫浦……………….……32
圖3.2.7 完整的具有正回授可增加交換速度的電荷幫浦………….…33
圖3.2.8 具有電荷幫浦的相位頻率檢知器的模擬結果,當ref領先local時,Vo充電上升…………………………………………………….…..34
圖3.2.9 具有電荷幫浦的相位頻率檢知器的模擬結果,當ref落後local時,Vo放電下降…………………………………………………….…..35
圖3.3.1 標準二階被動式迴路濾波器……………………………….…36
圖3.3.2 二階被動式迴路濾波器開迴路響應………………….….…...36
圖3.4.1 壓控振盪器特性圖…………………………………………….40
圖3.4.2 壓控振盪器具有可變電容負載架構………………………….41
圖3.4.3壓控振盪器具有可變驅動電容架構…………………….…….41
圖3.4.4 用偏斜延遲電路環形振盪器的基本觀念……………….……42
圖3.4.5 四輸入差動delay cell …………………………………….…..44
圖3.4.6 四級圖3.4.5的delay cell 組成的…………………….……...44
圖3.4.7 推薦使用的2.4GHz壓控振盪器的delay cell………….….…46
圖3.4.8 三級圖3.4.7的delay cell所組成的環形振盪器………..…...46
圖3.4.9 所推薦使用的2.4GHz壓控振盪器控制電壓與頻率的關係..47
圖3.5.1 P-C2MOS反相器和時脈虛擬NMOS反相器……………….49
圖3.5.2 N-C2MOS反相器和時脈虛擬PMOS反相器……………….50
圖3.5.3 新的TSPC具有比率技術D型正反器……………………..50
圖3.5.4 改良型TSPC比率D型正反器………………………….….51
圖3.5.5指出改良型TSPC比率D型正反器模擬時的波形圖……...51
圖3.5.6 除2的除頻器 …………………………………………..…..52
圖3.5.7除2的除頻器模擬時的波形圖…………………………..….53
圖3.5.8 除128的除頻器…………………………………………..…54
圖3.5.9 除128除頻器的模擬波形圖 …………………………..…..55
圖4.1.1 鎖相迴路將頻率鎖在2.4GHz…………………………..…..57
圖4.1.2頻率鎖在2.4GHz的頻譜………………………………..…..57
圖4.1.3本鎖相迴路鎖住的控制電壓……………………………..…58
圖4.1.4 2.4GHz鎖相迴路系統layout………………………….….58
表目錄
表3.1 所推薦使用的2.4GHz壓控振盪器和2.4GHz四輸入差動delay cell壓控振盪器的比較…………………………………………………..47
表4.1 所推薦使用2.4GHz鎖相迴路的模擬結果特性………………59

參考文獻
[1] Guan-Chyun Hsieh, J.C. Hung, “Phase-locked loop techniques. A survey, ’’
IEEE Transactions on Industrial Electronics, vol.43,no.6, pp. 609 —615 , Dec.1996.
[2] Lung-Chih Kuo, “1.5V 900MHz CMOS Phase-locked loop,’’ The Master's Thesis of the Department of Electrical Engineering,National Chung - Hsing University,
pp. 5 —10,44-47,Jun .2000.
[3] B.C. Sarkar, A. Hati, “Novel PLL-based frequency synthesiser without using the frequency divider,’’ IEE Proceedings- Circuits, Devices and Systems, vol. 148,no.5, pp. 255 —260 , Oct. 2001.
[4] Ya-Hui Liang, “A frequency synthesizer for bluetooth applications,” The Master's Thesis Department of Electrical Engineering,National Chung-HsingUniversity,pp. 33 —35,Jun. 2000 .
[5] M. Van Paemel, “Analysis of a charge-pump PLL: a new model, ’’IEEE Transactions on Communications, vol. 42,no.7, pp. 2490 —2498 , Jul.1994.
[6] J. McNeill, R. Croughwell, L. DeVito, A. Gasinov, “ A 150 mW, 155 MHz phase locked loop with low jitter VCO,” 1994. ISCAS '94. 1994 IEEE International Symposium on Circuits and Systems, vol. 3 , pp. 49 —52, May-2 June 1994.
[7] R.C. Chang,Lung-Chih Kuo, “A differential type CMOS phase frequency detector,’’ Proceedings of the Second IEEE Asia Pacific Conference onASICs,vol.5, 2000. AP-ASIC 2000, 2000.pp. 61 —64.
[8] Kwangho Yoon, Wonchan Kim, “Charge Pump Boosting Technique For Power Noise Immune High Speed PLL Implementation,’’ Proceedings of the 6th International Conference on Optimization of Electrical and Electronic Equipments, 1998. OPTIM '98., Vol. 3 , pp. 639 —642, May 1998.
[9] R.C. Chang, Lung-Chih Kuo; “A new low-voltage charge pump circuit for PLL,’’ The 2000 IEEE International Symposium on Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva, vol. 5 , pp. 701 —704,2000.
[10] E. Juarez-Hernandez, A. Diaz-Sanchez, “A novel CMOS charge-pump circuit with positive feedback for PLL applications,’’ 2001. ICECS 2001. The 8th IEEE International Conference on Electronics, Circuits and Systems, vol. 1 , pp. 349 —352,2001.
[11] E.J. Hernandez, A. Diaz Sanchez, “Positive feedback CMOS charge-pump circuits for PLL applications,’’ 2001. MWSCAS 2001.Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems, vol. 2 ,pp. 836 —839, 2001.
[12] Chan-Hong Park,Beomsup Kim, “A low-noise 900 MHz VCO in 0.6 μm CMOS,’’ 1998. Digest of Technical Papers. 1998 Symposium on VLSI Circuits, pp. 28 —29, Jun. 1998.
[13] W.S.T. Yan, H.C. Luong, “A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator,’’ Analog and Digital Signal Processing, IEEE Transactions on Circuits and Systems II: , vol. 48 ,no. 2 ,pp. 216 —221, Feb. 2001.
[14] Ching-Yuan Yang, Guang-Kaai Dehng; June-Ming Hsu; Shen-Iuan Liu; “New dynamic flip-flops for high-speed dual-modulus prescaler,’’ IEEE Journal of Solid-State Circuits, vol. 33, no. 10 ,pp. 1568 —1571, Oct .1998.

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