由於系統單晶片的時代來臨，傳統的特殊應用積體電路已不敷使用，因此如何將各種不同的演算法實現在相同的硬體中，以節省電路的面積及設計的時間。可重組化計算是相當熱門的研究領域之一，經由適當的調整，使硬體不再只是單一功能，能依照不同的應用以改變硬體。
在這篇論文中針對離散餘弦轉換轉換，提出一個二維雙模式之管線式離散餘弦轉換轉換器架構。專門用來處理8 × 8的區塊大小，以行列分離的運算是相當適合實現超大型積體電路，此架構包含兩種離散餘弦轉換轉換器，分別處理奇數及偶數的資料，利用可重組化管線化設計及兩種模式的切換，可以達到低功率及高速的需求，內部的字元長度所達到的精準度可滿足CCITT對於離散餘弦轉換的誤差需求，平行的規則架構也可達到高速運算的處理。
本晶片使用Artisan 0.25μm設計單元庫及TSMC 0.25 1P5M製程。晶片電晶體總數為77822，大小為1.38×1.38 mm2 ，最大操作頻率可達到56MHz。在56MHz的操作頻率下消耗功率為14.17mW；在28MHz的操作頻率下消耗功率為7.89mW。
在可重組化部分，提出一個適用於數位訊號處理的動態混合顆粒可重組化處器，此引擎包含一64個可重組化單元的陣列、控制器、可重組化資料緩衝器及微程式碼 ROM，可實現在視訊處理及訊號處理中常用的演算法。如離散餘弦轉換轉換、濾波器、FIR濾波器移動估計等演算法。在整個可重組化系統中扮演共同處理器的角色，以增加系統的效能。

In this thesis, we propose a cost-effective 2-D Discrete Cosine Transform IP Core with reconfigurable datapath.
The chip can process 8 × 8 block of video sequence. Even-odd decomposition is suitable for VLSI implementation.
The architecture includes of two types of reconfigurable processor to process even and odd data.
We use two mode operations of reconfigurable datapaths to achieve high speed and low power consumption.
The precision of wordlength can meet the requirement of CCITT standard.
A prototype chip is implemented in Artisan 0.25μm cell library and fabricated by TSMC 0.25μm 1P5M technology.
This chip includes a texture transpose memory, two DCT processors, pre-adder and the total transistor count is 77822. The die size is 1.38×1.38 mm2.
The operation speed of post-layout simulation can reach 56 MHz.
Static timing analysis is also used to verify the chip.
The power consumption is 14.17mW@56 MHz and 7.89mW@28 MHz.
Because of the approach of the decade of System-on-Chip (SOC), the traditional ASIC is inefficient to use.
Though how to map different algorithms in the same hardware, to reduce the hardware cost and design time is more important.
Reconfigurable computing is the latest research topic.
In this thesis, we propose a Reconfigurable DSP processor to
implement the algorithms of video processing and digital signal processing.
Such as Discrete Cosine Transform (DCT), motion estimation, FIR filter, and Discrete Fourier Transform (DFT).
The reconfigurable processor plays the role of co-processor in whole system to increase the performance of system.

Contents
1 Introduction 1
1.1 Recongurable Computing Overview . . . . . . . . . . . . . . . . 1
1.2 Classication of Recongurable Architecture . . . . . . . . . . . . 2
1.2.1 Recongurable Logic . . . . . . . . . . . . . . . . . . . . . 3
1.2.2 Recongurable Datapath . . . . . . . . . . . . . . . . . . . 3
1.2.3 Recongurable Arithmetic . . . . . . . . . . . . . . . . . . 3
1.2.4 Recongurable Control . . . . . . . . . . . . . . . . . . . . 6
1.3 Characteristic of Recongurable Architecture . . . . . . . . . . . . 7
1.3.1 Granularity . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.2 Depth of programmability . . . . . . . . . . . . . . . . . . 7
1.3.3 Recongurability . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.4 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.5 Computational model . . . . . . . . . . . . . . . . . . . . . 9
1.4 FPGA- based Architecture . . . . . . . . . . . . . . . . . . . . . . 11
1.4.1 Garp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4.2 DRLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5 Integrated Architecture . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.1 Morphosys . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.2 REMARC . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.3 PipeRench . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.4 RaPiD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.6 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2 Architecture Design of Dual-mode DCT IP Core 22
2.1 Discrete Cosine Transform algorithm . . . . . . . . . . . . . . . . 22
2.1.1 direct method . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.1.2 using other transform . . . . . . . . . . . . . . . . . . . . . 26
2.1.3 indirect method . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2 Modication of the DCT algorithm . . . . . . . . . . . . . . . . . 28
2.3 VLSI Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.4 Finite Wordlength Simulation . . . . . . . . . . . . . . . . . . . . 36
2.5 Low Power Consideration . . . . . . . . . . . . . . . . . . . . . . 37
3 Chip Implementation 39
3.1 Chip Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 Functional Verication . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.1 RTL verication of the DCT IP Core . . . . . . . . . . . . 41
3.2.2 Gate-level verication of the DCT IP Core . . . . . . . . . 42
3.2.3 Post-layout gate-level simulation of the DCT IP Core . . . 44
3.2.4 Post-layout transistor-level simulation of the DCT IP Core 44
3.3 Static Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . 48
3.4 Test consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.5 Implementation Result . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6 Hardware Emulation by Aptix MVP . . . . . . . . . . . . . . . . 56
3.7 Chip Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4 Architecture Design of Recongurable processor for Digital Sig-
nal Processing 62
4.1 Recongurable Computing Engine System . . . . . . . . . . . . . 62
4.2 Recongurable processor for DSP . . . . . . . . . . . . . . . . . . 63
4.2.1 Recongurable Cell . . . . . . . . . . . . . . . . . . . . . . 63
4.2.2 Split-ALU organization . . . . . . . . . . . . . . . . . . . . 65
4.2.3 Instructions for ALU/Controller . . . . . . . . . . . . . . . 69
4.2.4 Global Buses . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.2.5 Interconnection . . . . . . . . . . . . . . . . . . . . . . . . 70
4.3 Mapping algorithms and performance analysis . . . . . . . . . . . 72
4.3.1 Discrete Cosine Transform . . . . . . . . . . . . . . . . . . 72
4.3.2 Discrete Fourier Transform . . . . . . . . . . . . . . . . . . 73
4.3.3 Motion Estimation . . . . . . . . . . . . . . . . . . . . . . 75
4.3.4 FIR lter . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5 Conclusion 80
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